The roadmap for 0.2nm chips is disclosed for the first time.
Last month, imec, a semiconductor R & D institution in Belgium, released a R & D roadmap, which mainly outlined the development trends of semiconductor manufacturing technologies from the 2020s to the 2040s and highlighted several key technologies.
First of all, it should be noted that horizontal miniaturization reached its limit in the late 2010s. The trend of halving the SRAM cell area every two years (reducing the processing size by a factor of 0.7 every two years) continued until around 2010. After that, this trend slowed down to halving every four years, roughly from 2012 to 2018.
In addition, despite the continuous advancement of technology nodes since 2020, the cell area of SRAM has remained basically unchanged. For a standard 6 - transistor cell, its minimum area still ranges from 0.025 square micrometers to 0.023 square micrometers.
Trend of SRAM cell area reduction from 1998 to 2025
Even though horizontal miniaturization is approaching its limit, the pursuit of higher density and higher performance in semiconductor integrated circuits must continue. The demand for higher density and performance in the fields of artificial intelligence and high - performance computing remains strong.
Therefore, we are promoting the density improvement and performance enhancement of semiconductor devices through basic technologies such as "3D scaling" (considering not only the horizontal but also the vertical direction), introducing "new materials" in transistors and wiring, and "2.5/3D interconnection" technology. On the other hand, challenges such as the memory access bottleneck, the increasing difficulty of stable power supply, the sharp rise in power consumption, and the urgent need to strengthen heat dissipation technology hinder the performance improvement of artificial intelligence and high - performance computing systems. Therefore, the coordinated optimization of different technologies has become increasingly necessary.
Challenges in improving system performance and the coordinated optimization of new element technologies. The left figure shows new element technologies, and the upper figure shows the challenges in improving system performance
It is worth mentioning that in this roadmap, the chip roadmaps for 2A (0.2nm) and sub - 2A were disclosed for the first time.
Over the next 20 years, logic - based technology nodes will continue to improve
imec believes that the technology nodes of semiconductor logic devices will not only continue to develop in the 2020s but also extend to the 2040s. The technology nodes of semiconductor logic devices shown in imec's report span 28 years, from the "N7 (7 - nanometer) node" mass - produced in 2018 to the "sub - A2 (less than 2 angstroms) node" in 2046. Starting from this year (2026), the improvement of technology nodes will continue for another 20 years. The angstrom (Å) is a unit of length, one - tenth of a nanometer.
Looking at field - effect transistor (FET) technology, the N7 node in 2018, the N5 (5nm) node in 2020, and the N3 (3nm) node in 2023 all continued to use FinFET technology. Starting from the N2 node in 2025, nanosheet FETs (also known as GAA (gate - all - around field - effect transistors)) were selected. imec predicts that nanosheet FETs will be further improved and applied to the A14 (1.4nm or 14 angstroms) node in 2028 and the A10 (1.0nm or 10 angstroms) node in 2031.
Subsequently, in 2034, as the process node develops to A7 (0.7 nanometers or 7 angstroms), field - effect transistor (FET) technology will be replaced by complementary field - effect transistors (CFETs). A CFET is a transistor formed by vertically stacking p - channel nanosheet FETs and n - channel nanosheet FETs. Theoretically, the transistor density of CMOS logic circuits is expected to increase to 1.6 to 1.8 times that of nanosheet FETs. The improved CFETs will continue to be used in the A5 (0.5 nanometers or 5 angstroms) process node in 2037 and the A3 (0.3 nanometers or 3 angstroms) process node in 2040.
It is predicted that starting from the "A2 (0.2 nanometers or 2 angstroms) node" in 2043, "two - dimensional field - effect transistors (2D FETs)" will be used, in which the nanosheet - shaped channel material of CFETs will be replaced by "two - dimensional materials". 2D FETs will also be applied in the "sub - A2 node" in 2046.
Semiconductor logic technology roadmap from 2018 to 2046. This roadmap covers field - effect transistor (FET) technology and wafer back - side element technology
Wiring technology roadmap from 2025 to 2037
The process of manufacturing large - scale logic circuits on semiconductor wafers is roughly divided into front - end of line (FEOL) and back - end of line (BEOL). The FEOL is responsible for manufacturing transistors, while the BEOL is responsible for manufacturing multi - layer wiring. Usually, the wiring (multi - layer wiring) connecting transistors is formed after the transistors are manufactured. Therefore, the process sequence is to perform the FEOL first and then the BEOL.
The roadmap mentioned above mainly lists the transistor technologies developed in the front - end of line (FEOL) and their respective process nodes. imec also presented the back - end of line (BEOL) roadmap in its report. The time range of the BEOL roadmap is much narrower than that of the FEOL roadmap, extending from the 2nm node (N2 node) in 2025 to the A5/A3 nodes in 2037.
In 2025, the minimum pitch of the wiring technology for the N2 node is 24nm to 26nm, using copper (Cu) as the wiring metal and adopting dual - damascene and single - damascene processes. For the next - generation node, the A14 node in 2028, the minimum pitch will be reduced to 20nm to 22nm. This will be mainly achieved through improvements to the N2 node.
By the A10 node in 2031, the minimum wiring pitch will be further reduced to 18nm to 20nm. Ruthenium (Ru) is a popular candidate material for wiring metal, and air gaps are a popular choice for insulation between adjacent wirings. When using ruthenium wiring, the wiring forming technology will shift to subtractive manufacturing. The processing of vias (holes connecting layers) will use self - alignment technology.
The A7 node in 2034 aims to reduce the minimum pitch to 16nm - 18nm. This will be achieved through improvements in ruthenium metal, air gaps, and self - aligned via technology. The A5 node in 2037 aims to further reduce the minimum wiring pitch to 12nm - 16nm. The technology to achieve this goal is still under research and development.
Power technology roadmap from 2025 to 2032
imec also outlined its future outlook on the power technology of advanced packaging circuit boards for high - performance computing (HPC). The current power technology is to install multiple integrated voltage regulator (IVR) modules on the surface of the printed circuit board, reducing the power supply voltage from 48V DC to 12V DC and then further to 0.8V DC.
Current power technology for high - performance computing (HPC), with multiple integrated constant - voltage circuit modules installed on the circuit board surface
Between 2026 and 2027, a new power technology will emerge, which can integrate multiple integrated voltage regulator (IVR) systems into the circuit board. This will reduce the circuit board area and shorten the distance between the IVR and semiconductor chips (3D IC and HBM). The reduction of power circuit resistance and capacitance is expected to improve power efficiency and suppress noise.
The next - generation high - performance computing power technology is expected to be available between 2026 and 2027, with the IVR system integrated in the circuit board
In the future, integrated voltage regulators (IVRs) will be embedded in the packaging substrate, the interposer, and the back of semiconductor chips (3D IC). It is expected that high - performance computing (HPC) modules using such next - generation power technologies will be realized between 2028 and 2032. In addition, to improve efficiency and reduce noise, monolithic integration technology of power devices based on gallium nitride (GaN) on silicon (Si) and 2.5D high - capacity MIM capacitor technology using metal, high - dielectric - constant insulating films (insulators), and metal may be adopted.
The next - generation high - performance computing power architecture is expected to emerge between 2028 and 2032 (upper figure) and new basic technologies
Reduction of heat dissipation in the back - side power delivery network (BS - PDN)
Between 2028 and 2032, a power technology that has attracted much attention is the "back - side power delivery network (BS - PDN)" technology for silicon chips. Traditionally, both signal lines and power lines (including ground lines) are arranged on the front side of the wafer. To distinguish it from the BS - PDN, this arrangement is called the "front - side power delivery network (FS - PDN)".
In traditional FS - PDN technology, signal lines and power lines are mixed on the surface. The maximum current of power lines is much higher than that of signal lines. Signal lines can be made thinner through horizontal miniaturization. However, since an increase in current density will cause electromigration, which affects the lifespan of power lines, power lines cannot be made too thin. This limits the layout of signal lines.
Wiring structures of the traditional power delivery network (FS - PDN, left) and the next - generation power delivery network (BS - PDN, right)
Therefore, the BD - PDN moves the power network to the back side. The front side now only contains the signal wiring layer, which simplifies the layout and increases the signal wiring density.
The drawback of the BS - PDN is that its heat dissipation performance is significantly reduced. In the FS - PDN, the back - side circuit board acts as a heat dissipation channel. In the BS - PDN, except for the power lines, the thickness of the back side can be ignored. After removing the power lines, the heat dissipation channel is eliminated, resulting in a decrease in heat dissipation capacity.
Comparing the maximum operating temperature of the CPU core array, the FS - PDN remains at 90.7°C, while the BS - PDN rises to 104.3°C. The temperature increases by nearly 14°C.
Comparison of the maximum operating temperature of the CPU core array. The left figure shows the traditional power delivery network (FS - PDN), and the right figure shows the back - side power delivery network (BS - PDN)
Improving the heat dissipation performance of the back - side power delivery network (BS - PDN)
Therefore, we tried to improve the heat dissipation performance. We replaced the dielectric material connecting the front and back surfaces with a high - thermal - conductivity material and also replaced the thermal interface material (TIM) with a high - thermal - conductivity material. In addition, we reduced the thickness of the TIM. Through these measures, the maximum temperature dropped to 97.1°C.
Structure of the back - side power delivery network (BS - PDN). Before taking heat dissipation measures (maximum temperature 104.3°C)
Specifically, by replacing the traditional silicon dioxide dielectric material at the junction with aluminum nitride, the thermal conductivity increased by 40 times. Through this material replacement, the thermal conductivity of the thermal interface material increased by 1.33 times. The thickness of the thermal interface material was reduced to 60% of the original thickness.