Counter-trend TSV

For decades, the progress of semiconductor technology has been measured by continuously shrinking nanometer sizes. However, as the shrinking speed of transistor sizes slows down, the bottleneck has shifted from devices to interconnects, and advanced packaging has become the new frontier. The silicon interposer with through-silicon vias (TSVs) enables high-density 2.5D integration, shortens signal paths, and supports bandwidth far beyond what substrates and wire bonding can provide.

The next stage of development trend is counterintuitive: Larger TSVs (with a width of up to 50μm and a depth of up to 300μm) etched into thicker interposers can bring better electrical performance, more stable power transmission, better heat dissipation performance, and higher manufacturing yields.

From Wire Bonding to Interposers

This journey began with wire bonding, the standard interconnect technology in the 20th century. Subsequently, flip-chip packaging emerged, which reduced the interconnect size and parasitic effects (resistive, capacitive, and inductive effects that degrade signal transmission quality). However, even flip-chip technology cannot meet the growing demand for higher bandwidth and faster communication speeds between multiple chips. In the early 21st century, silicon interposers came into being, offering: redistribution layers (RDLs) for fine-pitch wiring; dense TSV arrays for vertical integration; and a platform for memory and logic integration. These advancements have driven the emergence of breakthrough technologies such as Xilinx FPGA Virtex 7, GPUs, and AI accelerators, and provided an evolving template for high-performance integration.

One of the most important innovations in the field of 2.5D and 3D integration is the introduction of TSVs (through-silicon vias) (Figure 1). TSVs are the vertical channels of modern semiconductor packaging - they are electrical interconnects that penetrate through silicon wafers, chips, or interposers, enabling direct communication between chips and efficiently transmitting power and signals between layers of 3D stacked chips or components on 2.5D interposers. Different from traditional wire bonding (which has longer paths and higher resistance), TSVs can form high-density vertical connections, thereby reducing signal delay, increasing bandwidth, and enhancing overall system performance.

An interposer is essentially a small piece of silicon or other substrate material that serves as an intermediate layer between silicon chips and printed circuit boards (PCBs). It plays a crucial role in connecting the microelectronic circuits of different chips and facilitating communication between them. By providing a high-density interconnect platform, interposers significantly enhance the functionality and performance of electronic devices.

Interposers for advanced packaging need to be custom-designed according to specific chip packages and packaging substrates. In this sense, interposers are very similar to bare circuit boards; they provide a platform on which the complete package will be assembled. All interposer designs aim to fulfill three important functions: providing a mounting surface for semiconductor chips in heterogeneous integration components, enabling connections between semiconductor chips, and reconnecting the entire stacked structure to the packaging substrate.

This structure contains a set of small vias (called through-silicon vias, or TSVs) and small pads for connecting semiconductor chips within the package. The interposer is connected back to the packaging substrate to facilitate further wiring between components and with the outside of the package. The bottom surface of the substrate contains an array of solder balls (BGA packaging), which can be assembled into the pad pattern on the PCB.

Between the TSV area and the microbumps on the top layer of the interposer is the redistribution layer (RDL). This layer contains the main horizontal interface connections for connecting the component chips on the top layer of the interposer. The interconnect structure in the RDL is similar to the blind/buried vias in HDI PCBs.

Interposers are usually made of three materials: silicon, glass, or organic substrates. Interposers are completely manufactured by foundries (TSMC is the main supplier), including through-silicon vias (TSVs) and horizontal interconnects bonded to the packaging substrate and semiconductor chips. Interposers can be designed to have two functions: as active devices or passive devices.

One of the main applications of silicon interposers is to connect high-bandwidth memory (HBM) to high-speed processors (Figure 2). Each HBM device itself is a 3D stacked structure built with TSVs, containing multiple DRAM chips and a logic layer. The transmission rate of a single HBM can reach up to 256 GB/s. The silicon interposer is the most efficient way to transmit data streams to the processor. Multiple HBMs can be integrated with a GPU on the same interposer, enabling a data transmission rate of 1TB/s or higher.

Why Bigger is Better

Although the manufacturing technology of TSVs has been developed for decades, its high process cost has limited the widespread adoption of TSVs beyond existing application areas. As the vias become narrower and deeper, the manufacturing cost also increases because deeper trenches require longer etching times, the deposition of continuous liner and barrier layer metals is more difficult, and the control of copper plating must be more precise to ensure the reliability of the connections. Therefore, equipment and material suppliers are working on producing stable and reliable TSVs for various applications while reducing costs.

The key consideration in the process is the mechanical and thermal stress exerted by TSVs on the surrounding area. The larger the aspect ratio of the via (the ratio of feature depth to diameter), the greater the tensile stress generated by the manufacturing process on the surrounding silicon wafer, which affects carrier mobility and thus the switching speed of transistors. This is the reason for what engineers call the "keep-out zone", the surrounding area where there must be no active circuits. However, as the number of I/Os increases and the TSV pitch decreases, the required keep-out zone is constantly shrinking. To some extent, chip layout is optimizing TSV layout from a system level (system-level co-optimization) to make more efficient use of precious silicon wafer space. Engineers are also exploring the causes of TSV proximity effects, which helps to minimize the size of this buffer.

However, to make the thicker interposer flatter and scalable to larger sizes, the aspect ratio of the TSVs must be higher, or the diameter of the TSVs must be larger. In fact, the aspect ratio has approached the limit of current manufacturing technology, and it is impossible to guarantee good yields and reasonable manufacturing time/cost. Therefore, the diameter of the TSVs must be increased. In addition to supporting larger interposer sizes, the advantages of larger-diameter TSVs include higher power transmission and lower high-frequency losses.

Currently, traditional TSVs (usually with a diameter of 5 - 10μm and a depth of 50 - 100μm) are transitioning to next-generation TSVs (with a diameter of up to 50μm and a depth of up to 300μm). Small TSVs are very suitable for low-frequency, low-power applications such as mobile communications and DRAM integration, but they have difficulty meeting the high requirements for current, heat dissipation, and bandwidth of applications such as artificial intelligence and high-performance computing (HPC). Their smaller size limits the current they can handle, leading to increased resistance losses and thus reduced signal integrity, especially under high-frequency operating conditions. In addition, the heat dissipation capacity of these small TSVs is limited, posing a significant challenge to heat-sensitive components.

Larger TSVs are designed for these types of environments. The advantages of larger TSVs include:

• Higher frequency – As the industry moves towards heterogeneous integration and multi-chip architectures, the demand for faster transmission between chips has increased significantly. Larger TSVs have a larger cross-sectional area, which can support higher data rates and enable parallel transmission of signals.
• Higher power transmission – Larger vias can carry larger currents with lower resistance, thereby reducing the IR drop and enabling faster communication between chips.
• Enhanced signal integrity – Wider TSVs can reduce inductance, which is crucial for high-frequency applications such as 5G.
• Heat dissipation management – Since TSVs act as heat pipes, larger vias can dissipate heat more effectively, protecting the stacked chips from thermal stress.
• Manufacturing robustness – A lower aspect ratio simplifies the deep reactive ion etching and copper plating processes, reducing the defect rate and increasing the yield.
• Improved assembly operations – Thicker interposers are less prone to cracking, making them more robust and durable to assemble.

Trade-Offs

Larger TSVs are not without challenges. For example, due to the mismatch in the coefficients of thermal expansion between copper (18ppm/°C) and silicon (2.8ppm/°C), the mechanical stress will increase, and this mismatch will intensify as the via size increases. In addition, since wider vias reduce the available wiring space on the interposer, the area will also be affected. Finally, larger TSVs increase material costs because each TSV requires more copper, which increases the electroplating time and thus the cost, although the increase in yield can offset some of the costs (Figure 3).

The expected application areas of larger TSVs include high-performance computing (HPC), such as servers and exascale supercomputers, which require massive bandwidth and reliable power supply. In addition, training large neural networks for artificial intelligence (AI) requires ultra-high-speed HBM links, and larger TSVs can provide stronger link stability. At the same time, low-latency, high-frequency 5G infrastructure systems require signal integrity, which small TSVs have difficulty meeting. Finally, automotive electronics for advanced driver assistance systems (ADAS) and autonomous driving systems require robust packaging and reliable heat dissipation performance, which larger TSVs can provide and ensure a longer service life.

Future interposers will integrate more functions and materials, such as the heterogeneous integration of CPUs, GPUs, memory, radio frequency, and photonic devices; new materials for combating copper stress and electromigration; embedded cooling through thermal vias, heat spreaders, or microfluidic technologies; and cost scaling to make TSV-enabled interposers cost-effective in consumer electronic devices.

The transition from TSVs with a diameter of 5 - 10μm to TSVs with a diameter of 50μm represents a fundamental shift in packaging concepts. By using larger and more robust vias, silicon interposers can meet the challenges of next-generation workloads in terms of frequency, power consumption, and heat dissipation. This evolution ensures the continuation of Moore's Law - not only in the shrinking of transistor sizes but also in smarter and more powerful packaging technologies.

This article is from the WeChat official account "Semiconductor Industry Observation" (ID: icbank), author: Chuck. It is published by 36Kr with authorization.