Another string of "code" from Lisa Su for AMD
In early November, AMD released an impressive Q3 financial report, in which its data center business recorded a single-quarter revenue of 8.546 billion US dollars, a year-on-year increase of 97%, accounting for 64% of total revenue, officially entering the "Data Center Era".
The two key business lines supporting AMD's "Data Center Era" are the Instinct series GPUs and EPYC processors.
Dr. Lisa Su, Chair of the Board and CEO of AMD, stated in the earnings statement that demand for Instinct series GPUs and EPYC processors remains strong, and growth will accelerate in the fourth quarter as production expansion of the Helios full rack system and "Venice" (6th Generation EPYC) ramps up.
At the "AMD In Depth" technology day held on November 4 local time in the United States, heads of business lines including EPYC elaborated on the new features of this year's EPYC product line, as well as the 8-year journey of the entire server CPU chip business from scratch, with gradually evolving performance that eventually helped AMD enter the "Data Center Era".
6th Generation EPYC evolution diagram from AMD official materials: from Naples in 2018 to Venice in 2026.
According to data disclosed by AMD, from Naples in 2018 to Venice this year, the throughput of a single SoC has increased by about 20 times.
The surge in performance has driven a sharp rise in data center business revenue. "At the beginning of the year, the server CPU share was just over 40%, and now it has reached the mid-40% range, with new customers switching to EPYC every week," said Madhu Rangarajan, Vice President of Server Products at AMD, in his opening remarks.
Dan McNamara, Senior Vice President of AMD and General Manager of the Compute and Enterprise AI Business Unit, said that revenue from both enterprise and cloud segments doubled year-on-year, "The 5th Generation Turin is the fastest ramping generation in EPYC history."
Post-earnings analysis from CNBC pointed out that relying on full-rack design and accumulated advantages in server CPUs, AMD is becoming the "second source" in the AI computing power supply chain of large technology companies.
In the past, GPUs captured most of the attention for computing power demand. Now, AMD hopes to use this technology day to elaborate on the role of CPUs in AI data centers in the era of models and Agents, and why CPUs are also the engine driving AMD into the "Data Center Era".
01 One CPU, Split into Four Platforms
The 6th Generation EPYC, codenamed Venice with the 9006 series model, shares the Zen 6 architecture, and is divided into Venice 9006 SP7, Venice 9006 SP8, Venice-X 9006X SP7, and Verano 9006 LP according to power consumption, memory, IO and cache, corresponding to different platforms for performance, enterprise, HPC and other scenarios.
Official materials split the 6th Generation EPYC into four platforms, corresponding to performance, enterprise, HPC and AI head node scenarios.
The first to ship is Venice SP7, which is also the flagship of this generation. It supports up to 256 cores and 512 threads when using Zen 6c cores, and up to 96 cores and 192 threads when using high-frequency Zen 6 cores; it is equipped with 16-channel DDR5, supports MRDIMM 12.8GT/s, and the official peak memory bandwidth is 1.6TB/s, which is about 2.6 times that of the 5th Generation's 614GB/s; it has 96 PCIe Gen 6 lanes for single-socket and up to 128 lanes for dual-socket configurations, all supporting CXL 3.1; the socket size is 76×80 mm, and the power consumption ranges from 400W to 600W.
SP8 is oriented to enterprise, storage, edge and telecommunications scenarios, with core counts ranging from 8 to 128. The number of memory channels is halved to 8 but each channel can support two DIMMs, while the number of PCIe Gen 6 lanes is even higher (128 lanes for single-socket, up to 192 lanes for dual-socket). The socket size is reduced to 62.5×80 mm with a maximum power consumption of 400W, and it is scheduled to ship in the first half of 2027.
AMD revealed that SP7 and SP8 use two different IO dies, which correspond to the computing power and IO requirements of the two types of markets respectively. This differentiated split comes from different customer demands - customers want a balance of performance per US dollar of the system, not just peak computing power.
Two more products are scheduled for the second half of 2027: Venice-X 9006X SP7 and Verano 9006 LP.
Venice-X supports 3D V-Cache - an additional SRAM cache die is vertically stacked above the CPU compute die, with the two layers bonded and packaged. It supports up to 96 cores with 1152MB L3 cache, the frequency still reaches 5.3GHz, and it is compatible with the SP7 socket, targeting cache-intensive technical computing scenarios such as EDA and CFD. Verano is a dedicated AI head node, which uses 24-channel LPDDR5X and field-replaceable SOCAMM modules, supports up to 192 cores, with the core goal of increasing the interconnection bandwidth between the CPU and AMD's own GPUs.
"You can't use one, two or three SKUs to support AI, because that can't deliver what customers really need," Dan McNamara explained the SKU split made against the background of differentiated customer demands.
In the view of Ravi Kuppuswamy, Senior Vice President of Compute and Enterprise AI at AMD, the agent pipeline can be split into different stages, and multiple links require CPU support, with varying dependencies on CPUs. "Agent AI is not a single type of workload, nor a workload that a single CPU can serve."
The demand differentiation is more obvious at the OEM partner roundtable.
On the second day of the technology day, at the OEM roundtable hosted by Derek Dicker, Corporate Vice President of AMD, Enterprise Business Group, the difference between AI budgets and traditional database workloads was mentioned, and it was emphasized that the two should not be split into isolated infrastructure pools.
"Not everyone needs a Ferrari. If what I need is a school bus, then I need a school bus, and you have to find a way to make the Ferrari and the school bus work well together," said John Carter, Vice President of Mainstream Computing at HPE.
From left to right: Derek Dicker, Corporate Vice President of AMD, Enterprise Business Group; David Schmidt, Vice President of Compute Infrastructure at Dell; John Carter, Vice President of Mainstream Computing at HPE; Scott Patty, Head of Product Management, Lenovo Infrastructure Solutions Group (ISG); Mike McNerney, Vice President of Marketing and Cybersecurity at Supermicro; Todd Brennan, Head of Data Center Product Management at Cisco
Mike McNerney, Vice President of Marketing and Cybersecurity at Supermicro, revealed: Based on the existing platform, the company has planned 20 SKUs. Some customers want more IO to connect GPUs and are willing to sacrifice memory capacity, while others prefer maximum memory capacity instead. Scott Patty from Lenovo also said that the same SP7 can be made into a 100% liquid-cooled fanless high-end HPC model, or a standard 2U single-socket server.
02 What Changes Have Been Made to Zen 6
"I won't pretend that I knew early on that agent computing would come, but we have always believed that CPUs will always have a place in the software stack," Mike Clark, Senior Vice President, Enterprise Fellow and Chief Architect at AMD, mentioned AMD's bet on the server CPU roadmap at the beginning of his speech.
For this generation of EPYC product line, the underlying architecture is the same Zen 6 architecture.
Mike Clark pointed out the design constraints of the new generation products: frequency, IPC (instructions per cycle), die area and power consumption are conflicting with each other. Pushing up the frequency will reduce the number of operations that can be done per cycle, and also consume more die area and power consumption. The approach for this generation is to continue widening on the new foundation laid by Zen 5: 8-wide dispatch, 6 ALUs, 4 memory operations per cycle, the operation cache is expanded from 6K instructions to 6.75K operations, the reorder buffer is increased from 448 entries to 640 entries, and the branch prediction return stack is increased from 52 entries to 64 entries.
This can be understood as AMD's approach to increase the number of instructions running simultaneously in the same clock cycle while maintaining the frequency, which is one of the benefits brought by the increase in transistor count under the 2nm process.
Official comparison: Zen 6c is optimized for per-lane throughput, while Zen 6 is optimized for minimum latency.
One CCD of Zen 6c is doubled from 16 cores of the previous generation to 32 cores, and L3 cache is increased from 32MB to 128MB; the CCD of high-frequency Zen 6 is increased from 8 cores to 12 cores with 48MB L3 cache. Both types of CCDs use TSMC's N2 process. As mentioned earlier, the reason why Venice-X has 1152MB L3 cache is the sum of 8 CCDs each with 144MB L3 cache.
In terms of frequency, Zen 6c is increased from 3.7GHz to above 4.1GHz, and Zen 6 is increased from 5.0GHz to 5.3GHz; under fixed frequency testing, IPC for enterprise and cloud workloads increases by about 20%, and that for AI workloads increases by about 31%.
However, Mike Clark emphasized that no single number can cover all workloads.
Official fixed frequency test: IPC for enterprise and cloud workloads increases by about 20%, and that for AI workloads increases by about 31%.
Stacking up to 256 cores is not the hardest part.
Mahesh Subramony, Senior Fellow and Corporate Vice President of AMD in charge of server architecture, said that they don't want customers to have to fill all 256 cores to get decent performance - in real workloads, these cores rarely run at full load at the same time, so the power budget has to be allocated between full load and half idle states.
At the same time, the power of the entire chip is not all allocated to the cores. The IO die, memory controller and inter-die interconnect take part of the power first, and the remaining part is shared by the cores.
In the early stage of architecture design, AMD expected that when all 256 cores run at full speed at 600W, each core will be allocated about 1.7W, and most of the performance figures announced on site are measured under this condition. But real workloads usually only have 30% of the cores running, with the total budget unchanged, idle cores do not consume power, so each running core can get about 3.5W. The extra power can be immediately converted into frequency, so even though Zen 6c is a density core, its frequency also needs to be pushed above 4.1GHz.
When switching to the 400W power consumption profile, the power budget per core is further reduced to slightly above 1W. At this time, only advanced processes and advanced packaging can minimize the power consumption of the rest of the chip, leaving as much share as possible to the cores. A technical Q&A also gave an estimation: moving 1TB/s bandwidth between dies consumes about 8 to 10W, while using ordinary packaging links to lay the same bandwidth will consume about 10% of the overall power budget.
"Power consumption is performance," Mike Clark said in the same technical Q&A session. If IPC increases by 20% while power consumption increases by 30%, that is a step backwards.
03 The Unavoidable Topic: Storage Cost
Over the past year or more, the demand for memory chips from AI servers has squeezed the supply of PC memory and pushed up prices.
Dan McNamara said in the Keynote the next day, "In ten conversations we had with enterprise customers, all ten were talking about memory, both about supply and cost." The PPT demonstrated on site also mentioned that for mainstream dual-socket servers, what determines the cost structure in 2026 is not the CPU, nor the GPU, but DRAM.
MEXT will greatly reduce servers' reliance on DRAM
To solve this problem, AMD has its own solution: MEXT, a technology developed by a company founded by former AMD employee Gary Smerdon (acquired by AMD in June 2026). You can understand MEXT as a technology that "virtualizes Flash as DRAM".
Gary Smerdon currently serves as Corporate Vice President of Compute and Enterprise AI Business Development at AMD. He revealed in his speech that the cost per GB of DRAM has dropped from about 50 million US dollars in 1974 to about 8 US dollars in 2012, and the recent shortage has pushed it back to about 50 to 60 US dollars per GB. DRAM conservatively accounts for 60% to 70% of server costs, and can reach 80% to 90% for large memory systems. However, a paper from Azure shows that half of the virtual machines never access more than half of their allocated memory.
Facing the high price situation, MEXT tries to reduce the reliance on DRAM through a pure software approach: the Linux driver transparently offloads cold pages (not accessed for more than 5 minutes) to a dedicated NVMe flash memory, and a set of AI models predicts which pages will be used soon and moves them back to DRAM in advance, making applications and operating