AMD Zen 6, officially launched, next-generation architecture revealed

In the early years, the construction of AI data centers was almost entirely centered around GPUs. From large model training to inference, GPUs have become the most sought-after computing chips across the entire infrastructure, while CPUs are mostly tasked with data preparation, task scheduling, and system management. Under this division of labor, server CPUs were once perceived as far less critical.

However, as AI evolves from large model training and inference to Agentic AI, the landscape is shifting. An Agent no longer merely receives queries and generates answers, but needs to continuously query databases, call APIs, retrieve context, execute code, use external tools, and coordinate across different tasks. A large volume of workloads does not run directly on GPUs, but requires continuous CPU involvement.

AMD believes this will reshape computing demands in data centers.

At the recent AMD In Depth event held in Las Vegas, the United States, AMD positions Agentic AI as a key driving force for the next round of growth in the server CPU market, forecasting that the data center CPU market will grow at a compound annual growth rate of over 50% in the future, with the market size expected to reach approximately 220 billion U.S. dollars by 2030. Forecast data cited by AMD also shows that by 2030, the number of active Agents deployed in production environments will hit 2.5 billion, a nearly 80-fold increase from current levels.

The changes in computing architecture demonstrated by AMD are also very intuitive: in the era dominated by chatbots, the configuration ratio of CPUs to GPUs was roughly 1:4; after entering the Agentic AI phase, this ratio is likely to approach 1:1, and there is still room for further growth. In other words, AI data centers no longer only need more GPUs, but also require more CPUs to support Agent operations.

Facing this shift, AMD is developing brand-new CPUs to embrace this upcoming era of drastic change. The newly disclosed Zen 6 architecture and the 6th-generation EPYC processor codenamed Venice are exactly the product layout designed around this change.

AMD Zen 6, Two Variants

As mentioned at the beginning of the article, in AMD's view, Agentic AI is not a single computing task. Different links may generate distinct computing demands, including not only CPU-intensive tasks, but also requirements for memory, I/O, security and accelerated computing. This also explains why AMD repeatedly emphasizes the role of CPUs in Agentic AI infrastructure: GPUs are responsible for model inference and accelerated computing, but for Agents to truly complete tasks, CPUs are required to handle scheduling, runtime environment management, data access and tool invocation. Especially when the number of Agents keeps growing, the number of concurrent tasks that CPUs need to process will also increase accordingly.

Therefore, to cater to different demands, AMD has brought two core designs this time: Zen 6 and Zen 6c.

According to the introduction, these two core designs are not simply trade-offs between core count and frequency, but are built to cover different computing requirements. In AMD's view, Agent Sandbox needs as many cores and threads as possible to run more Agents simultaneously; GPU Host nodes prioritize high frequency and low latency, requiring CPUs to feed data to GPUs in a timely manner to avoid idling of expensive accelerators while waiting for data.

Based on the above insights, AMD positions Zen 6 as an architecture primarily targeted at workloads that are more sensitive to single-core performance, frequency and response latency. In its introduction, AMD defines it as "Optimized for lowest latency". Compared with the previous-generation Zen 5, the number of cores per CCX of Zen 6 has increased from 8 to 12, a single CCD integrates up to 12 cores, and the total L3 cache has increased from 32MB to 48MB, still maintaining 4MB L3 cache per core. In terms of frequency, the maximum frequency AMD provides has increased from 5.0GHz on Zen 5 to 5.3GHz. At the same time, Zen 6 also delivers a significant IPC uplift, as well as improvements in power efficiency and SMT efficiency.

Thanks to this design, AMD Zen 6 is more suitable for scenarios with high requirements for high frequency and low latency, such as GPU Host nodes. CPUs need to complete task scheduling and data preparation in a timely manner, and feed data to GPUs to avoid idling of GPU computing resources caused by waiting for CPUs.

As for Zen 6C, it is mainly oriented to cloud computing and large-scale parallel computing scenarios, and AMD positions it as "Optimized for maximum socket performance". As shown in the figure, compared with the previous-generation Zen 5C, Zen 6C increases the number of cores per CCX from 16 to 32, doubling the core count; the total L3 cache increases from 32MB to 128MB, which is 4 times that of the previous generation. According to data disclosed by AMD, each core of Zen 6C has 4MB of L3 cache, while that of Zen 5C is 2MB. In terms of frequency, the maximum frequency of Zen 6C has increased from 3.7GHz on Zen 5C to 4.1GHz. AMD also highlights the IPC performance improvement of large cores, as well as improvements in power efficiency and SMT efficiency.

AMD states that the advantage of Zen 6C lies in its ability to integrate more cores in a single processor, thereby improving the parallel processing capacity of single-socket servers. For Agent Sandbox, cloud computing and large-scale concurrent tasks, this means one server can carry more workloads, reducing the number of servers and corresponding deployment costs.

During the sharing session, AMD demonstrated the IPC performance improvement of the Zen 6C architecture compared to Zen 5. As shown in the figure below, AMD uses a fixed-frequency test, with 16 cores as the benchmark, to compare the scenario where Zen 5 uses two CCDs to carry 16 cores and the scenario where Zen 6C uses a single CCD to carry 16 cores. In enterprise and cloud server workloads, Zen 6C delivers a geometric mean IPC improvement of approximately 20%. In AI workloads, using the same fixed-frequency 16-core comparison method, Zen 6C achieves a geometric mean IPC improvement of around 31% compared to Zen 5.

Combining AI and server workloads, AMD gives a geometric mean IPC improvement of approximately 27% for Zen 6C. This set of data reflects an important positioning of AMD for Zen 6C: while increasing core density, it does not sacrifice single-core performance, but delivers significant IPC improvements across different types of server workloads.

All-New EPYC, Ushering in a New Era

Along with the debut of Zen 6, AMD also revealed in-depth details of the 6th-generation EPYC processor (codename: Venice) built on TSMC's 2nm process.

As for the design aspect, as always, AMD adopts the Chiplet design on Venice, but the entire SoC consists of up to 8 compute dies (CCDs) and 2 I/O dies (IODs). Compared with the previous generation platform, AMD further adjusts the inter-chiplet connection method and I/O layout to meet the higher requirements for data transmission, memory bandwidth and external connectivity brought by the increased number of cores. Among them, CCDs are responsible for computing, while IODs handle functions including Fabric, memory controllers, PHY, I/O control and security.

First, looking at the CCD, as introduced, this generation of products is built using TSMC's 2nm process. As mentioned above, on this generation of products, AMD has implemented its first upgrade since Zen 3 — the standard Zen 6 CCD can now scale up to 12 cores, while Zen 6c has 32 cores. In comparison, the maximum core counts of CCDs for Zen 5 and Zen 5c are 8 and 16 respectively. In addition, AMD has doubled the shared L3 cache capacity per core for the Zen 6c CCD, and since its core count has doubled, the L3 cache capacity has actually increased fourfold compared to Zen 5c.

Moving to the I/O Die built on 6nm process, AMD adopts a dual-IOD separate design on Venice. Each IOD integrates 8 DDR5 memory channels, and the two IODs provide a total of 16 channels, supporting MRDIMM up to 12.8GT/s, with the theoretical maximum memory bandwidth of a single-socket processor reaching 1.6TB/s. Each IOD is also equipped with 48 64G SerDes and 8 16G SerDes, and the two IODs provide a total of 96 64G SerDes and 16 16G SerDes. AMD states that the adoption of the dual-IOD layout is mainly to cope with higher memory channel counts, larger bandwidth and more complex I/O requirements, while improving QoS and data traffic distribution.

Interconnection between chiplets is also a key upgrade for Venice. AMD enhances the data path from CCD to IOD to improve the processing capacity for data response and write-intensive traffic, while increasing the number of ports to boost bandwidth and data sharing capabilities. In addition, Venice uses Elevated Fanout Bridges (EFB) to implement Die-to-Die communication. AMD claims that this method can reduce the unit energy consumption of data transmission between chiplets, further lower latency, and release more power headroom for processor cores. The platform also adopts the 5th-generation Infinity Fabric and supports faster Fabric P-state switching to improve energy efficiency performance.

In addition to architectural innovations, the AMD Venice series also has a major shift: it no longer follows the single-platform strategy, but launches two major platforms SP7 and SP8 with different physical interfaces, and further lays out two segmented product lines 9006X (Venice-X) and 9006 LP (Verano) to address different demands.

Among them, the embedded 9006 series SP7 CPU offers up to 256 cores and 512 threads, with multiple SKUs ranging from 64 cores to 256 cores to meet the performance, power consumption and frequency requirements of different applications. In terms of memory, this series is equipped with 16 DDR5 memory channels, supporting RDIMM up to 8000MT/s and MRDIMM up to 12800MT/s. In terms of I/O, it provides up to 96 PCIe Gen 6 channels with a per-channel rate of 64GT/s, and supports CXL 3.1 at the same time, providing connectivity for high-speed storage, network devices, accelerators and memory expansion devices.

Data released by AMD shows that compared with the previous-generation EPYC embedded 9005 series, the overall throughput of the 9006 series is improved by up to 1.8 times, I/O bandwidth by up to 1.5 times, and memory bandwidth by up to 2.7 times. In terms of applications, AMD focuses on semiconductor automated test equipment (ATE), enterprise storage and network firewalls. In the field of semiconductor testing, the processor can undertake control and orchestration tasks for test systems, supporting more tests to run in parallel; in the field of network security, it can be used for the control plane of 400G/800G firewalls, with related throughput improved by up to 1.3 times; in the field of enterprise storage, it can accelerate NVMe device management as well as data processing tasks such as compression, caching and RAID, with ISA-L related test performance improved by up to 1.5 times.

Considering that embedded devices usually require long-term deployment, AMD provides a seven-year product supply cycle for the EPYC embedded 9006 series, with continuous firmware update and software support. In terms of security, this series integrates security mechanisms including AMD Root of Trust (ART), AMD Secure Processor (ASP) and Caliptra, covering secure boot, runtime protection and device identity authentication, and also supports post-quantum cryptography technology for firmware signing.

Full-Scale Expansion, Disclosing New Roadmap

Actually, during the two-day sharing session, AMD disclosed a large amount of information about chips, which is far beyond what the above content can summarize. In addition, the company has made comprehensive layouts in systems and software to better serve customers. For example, in AMD's view, there is no one-size-fits-all standard rack solution for Agentic AI infrastructure. Deployments of different scales, existing data center conditions and workload characteristics determine that customers have different demands for CPU, GPU configurations and cooling methods.

To this end, AMD provides three different Agentic Rack configurations via Helion, targeting the hyperscale data center and enterprise markets respectively.

The first one is the Agentic Rack for large cloud service providers and hyperscale data centers, which adopts a separate deployment of CPUs and GPUs, where the CPU rack uses a direct liquid cooling design to improve rack power density and computing deployment density. The second one is for enterprise customers who want to