NVIDIA has entered the CPU market, is it set to upend the Chiplet landscape?
Why did NVIDIA go "against the trend"?
When looking at the architecture choice of NVIDIA's Vera CPU, many people may have such a question.
Over the past few years, Chiplet (multi-die) technology has gradually become a critical design path for high-performance server CPUs, and numerous manufacturers have joined this trend one after another.
Contrary to this trend, the recently launched Vera CPU from NVIDIA chooses to integrate 88 CPU cores, unified L3 cache and on-die interconnection on the same computing die, adopting a monolithic computing die design.
Against the background that Chiplet has gradually become the mainstream, why did NVIDIA choose a different path? What kind of performance and manufacturing trade-offs are involved behind this choice?
NVIDIA's Considerations
In March 2026, NVIDIA officially released the Vera CPU at the GTC conference, positioning it as a new-generation processor for AI agents, reinforcement learning and data processing. As AI applications gradually involve tool calling, code running, data retrieval and complex task execution, CPUs need to take on more work of program execution and task scheduling, and their processing speed will also affect whether GPUs can continue to operate efficiently.
Vera adopts a monolithic computing die design, integrating 88 Olympus CPU cores, 164MB unified L3 cache and the second-generation Scalable Coherence Fabric (SCF) on the same computing die. The SCF is responsible for connecting CPU cores and shared cache, with the maximum on-die bidirectional bandwidth reaching 3.4TB/s. The memory and I/O subsystems are implemented by components such as adjacent independent dies.
Why did NVIDIA choose this design?
In an exclusive interview, the Vera team talked about the changes in the design priorities of data center CPUs. As the scale of cloud computing expands, processor design pays more and more attention to the number of cores and overall throughput, and die partitioning has also become an important way to expand processor scale. The NVIDIA team believes that this trend has to a certain extent reduced the priority of single-threaded performance in design, while the rise of AI agents has refocused attention on the execution efficiency of individual cores.
When an agent executes tasks, it often needs to continuously call tools, run code, query databases, and then decide the next action according to the results. These processes include serial operations, branch judgments and data access, and some steps must wait for the completion of previous tasks. Therefore, even if the server can run a large number of tasks in parallel, the execution speed of a single task will still affect the entire workflow. NVIDIA hopes that Vera can complete these CPU-side tasks faster and reduce the waiting time for critical steps.
The monolithic computing die provides a design idea for this purpose. Since the computing cores, unified L3 cache and on-die interconnection are located on the same die, all cores can exchange data through a unified on-chip network, reducing the extra overhead caused by cross-computing-die communication. NVIDIA also improves execution efficiency through the microarchitecture of the Olympus core itself, including designs such as a 10-wide instruction fetch and decode front-end, a neural network branch predictor and deep out-of-order execution, and optimizes data access combined with a cache prefetch mechanism. The core microarchitecture and on-die interconnection work together to jointly affect the actual performance of the processor.
Of course, this design also has its costs. Concentrating 88 computing cores, large-capacity cache and interconnection on a single die will increase the die area and design complexity, and manufacturing yield and cost control will also face higher requirements. Compared with the multi-chiplet solution, the monolithic computing die has relatively limited flexibility in computing module reuse, core scale combination and adopting different process nodes for different functions.
The NVIDIA team also stated that the company will choose the integration solution according to specific product requirements. The design priority of the Vera CPU is to tightly integrate the computing part to meet the requirements of workloads such as AI agents for single-threaded performance, communication efficiency and low latency, while accepting the constraints of large-area computing dies in manufacturing and scalability.
What are the trade-offs of mainstream CPU integration paths?
Looking at the entire CPU market, NVIDIA's choice of Vera is only one of the current high-performance CPU integration architectures. Companies such as AMD and Intel are also exploring different chip design methods. Although these designs are all pursuing higher integration and processor performance, each company has different considerations for the arrangement of internal chip functions.
AMD: Based on the Zen architecture, continuously advancing Chiplet integration
AMD is one of the manufacturers that applied Chiplet to mainstream CPU products on a large scale at an early stage. Its Zen architecture has gradually formed a modular design path based on computing dies. By separating CPU computing cores from I/O functions, and then using different die combinations to achieve processor scale expansion. This design has been more widely used since the Zen 2 period, and has gradually become an important architectural foundation for AMD Ryzen and EPYC series high-performance processors.
In terms of specific implementation, AMD organizes multiple CPU cores in CCX (Core Complex), and then integrates them on the CCD (Core Complex Die). Multiple CCDs connect external interfaces such as memory controllers and PCIe through the central I/O die (IOD), and complete data transmission and cache coherence management between different computing dies through Infinity Fabric interconnection technology.
Taking the EPYC 9005 series as an example, AMD provides server processors with different core scales by configuring different numbers of CCDs. After the computing cores and I/O functions are designed separately, AMD can adjust the number of computing dies according to product requirements, and also allow different modules to adopt manufacturing processes that are more suitable for their own functions. This modular method improves the reuse rate of computing design and provides greater flexibility for processor product expansion.
On this basis, AMD has further explored vertical stacking technology. Taking 3D V-Cache as an example, AMD stacks an additional L3 cache die on top of the computing die through through-silicon vias (TSVs) and copper-to-copper direct bonding, increasing cache capacity in a limited packaging space. Compared with simply increasing the number of computing dies, this method expands the chip's integration capability in the vertical direction.
AMD also extends Chiplet technology to heterogeneous integration. Taking the Instinct MI300A as an example, AMD integrates Zen 4 CPU computing dies, CDNA 3 GPU computing dies and HBM3 memory in the same package to realize unified memory access between CPU and GPU. Dies with different functions can adopt their own suitable design and manufacturing methods, and then be combined into a complete computing system through advanced packaging.
From the computing die modularization of the Zen architecture, to the vertical cache stacking of 3D V-Cache, and then to the heterogeneous integration of CPU, GPU and HBM of MI300A, AMD continues to expand the application of Chiplet in different products. Its technical route has also gradually extended from the horizontal expansion of computing cores to cache stacking and the integration of multiple computing units.
Intel: Splitting Tiles by function and process nodes, combining through advanced packaging
Intel's Chiplet layout is mainly centered on the Tile architecture. A Tile can be understood as an independent silicon module that undertakes specific functions. Intel organizes functions such as computing, memory and I/O inside the processor into different Tiles, and then combines them into a complete CPU through packaging interconnection. Starting from the Xeon 6 series, Intel has fully adopted the modular Tile architecture, and both P-core and E-core products adopt the combination of computing Tiles and I/O Tiles, with specific quantities varying according to product models.
Taking the Xeon 6 P-core series Granite Rapids as an example, Intel configures different numbers of computing Tiles according to processor models. Taking the Granite Rapids AP architecture as an example, it adopts 3 computing and memory Tiles and 2 I/O Tiles. The computing and memory Tiles integrate CPU cores, cache and memory controllers, responsible for main computing tasks and memory access; the I/O Tiles are responsible for external high-speed interfaces such as UPI, PCIe and CXL, as well as part of data processing acceleration functions. Different Tiles undertake corresponding tasks respectively, and then complete data exchange through the interconnection inside the package.
Splitting Tiles by function allows Intel to adjust computing resources and Tile configurations according to product positioning, while combining different manufacturing processes. In the Granite Rapids AP architecture, the computing and memory Tiles use the Intel 3 process, and the I/O Tiles use the Intel 7 process. CPU computing cores have high requirements for transistor density, performance and energy efficiency, and adopting a more advanced process helps to improve the performance of the computing part; the I/O part can select the corresponding process according to interface and data transmission requirements. In this way, Intel can optimize different functional modules separately, reducing the manufacturing cost pressure caused by all modules relying on the most advanced process.
As the number of Tiles increases, data exchange between dies also puts higher requirements on packaging interconnection. To this end, Intel uses EMIB (Embedded Multi-die Interconnect Bridge) technology to connect different Tiles. Its core is to embed small silicon bridges in the packaging substrate. The silicon bridge is equipped with multi-layer metal wiring inside, and the chip is connected to the silicon bridge through micro-bumps, so as to establish high-density interconnection channels between different dies. Compared with solutions using large-area silicon interposers, EMIB only sets silicon bridges at positions that require high-speed interconnection, reducing the demand for large-area silicon interposers, which is conducive to controlling the packaging structure and cost, while supporting high-bandwidth communication between multiple dies. Intel has also developed Foveros vertical stacking technology, and explored the combination of EMIB and Foveros in other packaging solutions to further expand multi-die integration methods.
Arm: Advancing open computing subsystems and dual-die CPUs in parallel
Arm's Chiplet layout has its particularity. For a long time, Arm mainly provides CPU core IP and computing subsystems to chip design enterprises, helping partners develop their own processors. Therefore, Arm's layout in the die field mainly focuses on pre-integration of computing modules, interface configuration and open ecology. In recent years, Arm has also begun to extend its business to its own chip products, exploring different die integration methods.
Among them, Neoverse CSS (Compute Subsystems) is a pre-integrated computing platform launched by Arm for the data center and server market. It integrates Neoverse CPU cores, Core Mesh Network (CMN), memory, I/O and related control modules, and has undergone configuration, verification and performance optimization. On this basis, partners can adjust the number of cores, memory configuration and I/O interfaces according to product requirements, and then add their own designed functional modules to develop customized processors.
In terms of die interconnection, Neoverse CSS supports inter-die interconnection interfaces such as AMBA CHI C2C, which can be used for multi-chiplet processors and heterogeneous computing systems. Arm also cooperates with chip design, EDA tool, wafer manufacturing and packaging enterprises through the Arm Total Design ecology to provide partners with support from IP integration to chip manufacturing. This method can reduce the design and verification work required for customers to build computing subsystems from scratch, and accelerate the development process of customized chips.
In March 2026, Arm officially released the Arm AGI CPU, which is Arm's first mass-produced chip product in its more than 35 years of history, marking that its business has further extended from providing processor IP and computing subsystems to complete CPU products. The Arm AGI CPU is built based on Neoverse V3 CSS, targeting AI data center and agent workloads, and provides different configurations of 64 cores, 128 cores and 136 cores.
In terms of chip integration, the Arm AGI CPU adopts a dual-die design. According to the architecture information disclosed by Arm at Hot Chips 2026, each die integrates Neoverse V3 CPU cores, six-channel DDR5 memory subsystem and related I/O functions. The two dies are connected through UCIe interconnection, and the entire processor provides up to 12 channels of DDR5 memory. Each die also adopts the CMN-S3 mesh interconnection network, which is responsible for connecting resources such as CPU cores, memory and I/O. The total bandwidth of the UCIe interconnection between the two dies reaches 2TB/s.
One feature of this design is that the computing cores and local memory resources are placed in the same die. Local computing cores can directly access the connected memory resources, reducing the dependence of part of data access on cross-die communication. For data center workloads that are sensitive to memory bandwidth and access latency, this organization method helps to improve local memory access efficiency.
For the dual-die architecture, data exchange across dies still needs to be handled. If a computing core needs to access the memory connected to another die, the data request needs to be transmitted through the UCIe interconnection, and the access latency will increase accordingly. Therefore, Arm organizes memory access between the two dies through the CMN-S3 coherence interconnection and NUMA (Non-Uniform Memory Access) architecture, so that computing cores can access local and remote memory resources. For local memory access, data can be directly provided by the memory subsystem of the die where it is located. When it is necessary to access the memory of another die, data transmission is completed through inter-die interconnection.
NVIDIA: Advancing monolithic die and multi-chip interconnection in parallel
Back to NVIDIA. The choice of Vera this time does not mean that NVIDIA will completely "reverse" back to the monolithic design path.
Looking back at its data center CPU product layout, NVIDIA has been exploring the design idea of combining monolithic die integration with multi-chip high-speed interconnection.
Taking the Grace series as an example, a single Grace CPU adopts a monolithic die design, integrating 72 Arm Neoverse V2 cores, 114MB L3 cache, and NVIDIA's self-developed Scalable Coherence Fabric (SCF) on the same die. The SCF adopts a mesh interconnection structure, which is responsible for connecting resources such as CPU cores, cache, memory and system I/O, providing support for data exchange inside the processor.
On this basis, NVIDIA further launched the Grace CPU Superchip, which connects two independent Grace CPUs through NVLink-C2C high-speed interconnection technology to form a processor module with 144 CPU cores, with a bidirectional interconnection bandwidth of 900GB/s. NVLink-C2C supports cache coherence between the two CPUs, enabling them to share data and memory resources and process computing tasks collaboratively.
Which links do different integration paths affect exactly?
The first is data transmission efficiency. The computing cores inside the CPU need to frequently access cache and memory, and exchange data with other cores. The integration method of functional modules directly affects the data transmission path. The monolithic design concentrates computing cores, shared cache and on-die interconnection on the same die, and data can be transmitted through the on-chip network, reducing the latency and power consumption of cross-die communication. The multi-chiplet design needs to complete data exchange through inter-die interconnection, which adds interface circuits and packaging interconnection links, and also brings additional communication overhead. Therefore, for workloads that require frequent data exchange between cores and high shared cache access requirements, tight integration of computing resources has advantages.
The second is manufacturing process and cost. The monolithic design needs to integrate more functions on the same die. The larger the die area, the higher the risk of being affected by defects in the manufacturing process, and the more difficult it is to control the yield. Chiplet splits a large chip into multiple smaller dies, which can improve the manufacturing yield of a single die, and allow different functions to adopt different process nodes. For example, computing cores can adopt advanced processes, while functions such as I/O can adopt mature processes, thus reducing the dependence of non-core computing parts on advanced processes. This separation of function and process allows chip manufacturers to arrange manufacturing resources more flexibly.
The last is product expansion and design reuse. The monolithic design needs to concentrate more functions on the same die. When the number of cores, cache capacity and I/O configuration change, it is often necessary to re-adjust the overall chip design. Chiplet can develop and manufacture functional modules such as computing, memory and I/O relatively independently. Manufacturers can form products with different core scales by adjusting the number of computing dies, and can also retain mature I/O modules when upgrading computing cores, reducing redundant development work. This modular design helps to shorten the product iteration cycle and provides more combination space for the development of processors with different specifications.
From data transmission and manufacturing processes to product development, chip integration methods will affect the performance, cost structure and product iteration efficiency of CPUs. The monolithic design pays more attention to the close collaboration between computing resources, while Chiplet provides more space for function splitting, process matching and module reuse.
Conclusion
From the current development of high-performance CPUs, Chiplet will still be an important technical route, especially with advantages in core scale expansion, design module reuse and combination of different process nodes. However, the monolithic computing die still has its application space. For computing parts with frequent inter-core communication and high shared cache access requirements, centralized integration can still bring advantages in latency and communication efficiency. In the future, monolithic design and multi-chiplet integration may also be combined and used in the same processor.
With the development of advanced packaging and die interconnection technology, CPU architecture design will further develop towards refined function division. Manufacturers can decide which computing resources need tight integration and which functions are suitable for independent manufacturing according to different application scenarios, and then realize different product requirements through customized die combinations. The competition of CPU integration architectures in the future will be more reflected in the organization of functional modules, the interconnection performance between dies, and the efficient collaboration that different modules can achieve.
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