Transistors Beyond the 1nm Node: Four Industry Titans Vying for Hegemony
For two decades, the semiconductor industry has continuously reshaped transistor structures to keep pace with Moore's Law: evolving from planar transistors to FinFET (Fin Field-Effect Transistor), and now to GAA (Gate-All-Around) nanosheet structures. Each technology iteration has brought roughly a decade of development space for chip miniaturization.
At present, as leading logic chip manufacturers bring nanosheet processes into mass production, a brand-new transistor architecture — CFET (Complementary Field-Effect Transistor) — has become the focus of attention at IEDM (International Electron Devices Meeting) and the VLSI Symposium (Symposium on Very Large Scale Integration Circuits and Technology).
CFET no longer places n-type and p-type transistors side by side, but stacks them vertically on top of each other (Figure 1). Its core concept is very intuitive: a standard CMOS inverter requires one NMOS and one PMOS device arranged side by side, which takes up corresponding area on the wafer; through vertical stacking, CFET can theoretically achieve the same logic function in about half the horizontal area (Figure 2).
At present, many chip manufacturers regard CFET as the key architecture to push logic chip miniaturization beyond the 2nm node and into the "sub-1 nanometer" era. Over the past three years, Intel, TSMC, Samsung and IBM Research have all demonstrated the feasibility of this architecture through actual silicon wafer verification.
Two Paths to the Same Stacked Structure
There are two main ways to build CFET (Complementary Field-Effect Transistor), and the industry has not yet reached a consensus on one of them.
In the "monolithic integration" process, the bottom and top transistors are constructed sequentially on the same wafer through consecutive process steps — that is, the bottom device is fully fabricated first, and then the channel material and gate stack of the top device are formed above it. This method simplifies the overall process flow, but at the cost that the completed bottom transistor must withstand all the thermal treatment and etching steps required to build the upper device.
In the "sequential integration" process, the bottom and top transistors are fabricated on separate wafers (usually at different stages of the process, sometimes even using different channel materials), and then bonded together. Sequential integration eases the "thermal budget" challenge, but adds wafer bonding, alignment, and additional lithography steps.
To date, most of the solutions demonstrated by TSMC, Samsung and Intel adopt monolithic integration; while IBM Research has formulated its technology development roadmap around the sequential integration route, which will be further discussed below.
First Demonstration: IEDM 2023
At the IEDM (International Electron Devices Meeting) held in December 2023, CFET (Complementary Field-Effect Transistor) technology evolved from a concept on PPT slides to functional devices. Intel, Samsung and TSMC all presented their relevant data at the conference — this was the first time the three companies had presented CFET research results at the same conference.
Intel demonstrated a complete inverter circuit (rather than an isolated device). The circuit adopts a contact poly pitch (CPP) of 60nm, each device contains three stacked nanosheets (compared to two in previous studies), and the device spacing is also reduced from 50nm to 30nm. Intel also combined this demonstration with "backside power delivery" technology — connecting the bottom transistors from the underside of the wafer, instead of laying both power lines and signal lines above the devices. Intel stated that at full scaling, the area of this CFET inverter can be reduced to about half of the area of an equivalent side-by-side CMOS inverter.
In its 3D stacked field-effect transistor (3DSFET) architecture, Samsung demonstrated structures with a single nanosheet per device pair at 45nm and 48nm gate pitch (CPP). The company also reported that the process for isolating the source and drain regions between stacked devices has changed from wet chemical etching to dry etching; according to Samsung, this improvement has increased device yield by about 80% compared with the previous method (see Figure 3).
In its 48nm gate pitch (CPP) solution, TSMC adopted a layer of high-germanium-content silicon germanium (SiGe) material, which enables the isolation regions between stacked nanosheets to be etched away at an earlier stage of the process flow (i.e., before the final nanowire release step). This adjustment of the process sequence is designed to protect the formed isolation layer from the influence of subsequent high-temperature process steps. At that time, the industry estimated that the commercial mass production of CFET (Complementary Field-Effect Transistor) would take 7 to 10 years — subsequent published papers have largely confirmed this forecast.
Progress Report: IEDM 2024
One year later, the relevant technology has evolved from isolated devices to functional logic gates that can actually operate.
Sandy Liao, TSMC's Director of R&D Exploration, demonstrated what the company called the first fully functional CFET (Complementary Field-Effect Transistor) inverter; the inverter was fabricated using a monolithic integration process with a gate pitch of 48nm. These devices exhibit balanced voltage transfer characteristics at voltages up to 1.2V; the subthreshold slopes of both n-type and p-type devices are 74–76 mV/decade — these figures are quite impressive for the first operable circuit and are close to the technical indicators required for mass production nodes.
Samsung and IBM Research jointly demonstrated a variant of the standard CFET stacked structure: instead of designing the top and bottom channels to the same width, the devices adopt a "stepped" structure — the bottom NFET contains two wider nanosheet channels, while the top PFET contains three narrower channels. According to Chen Zhang from IBM, this stepped geometry "alleviates the challenges brought by high-aspect-ratio processes by reducing the total stack height", while delivering better performance than equal-width stacked structures under the same footprint. In addition, the wider bottom channel provides a more direct "line-of-sight" path for process equipment to form contacts on the lower-layer devices — one of the most difficult steps in the CFET manufacturing process.
Intel did not release new CFET data at the 2024 IEDM, despite having presented relevant results in the previous two years. This "absence" attracted some attention, but judging from the company's subsequent papers published at the VLSI Symposium, this is more of a temporary pause than a change in technical direction.
VLSI 2026: More Clear Focus
At the 2026 VLSI (Symposium on Very Large Scale Integration) Technology and Circuits Symposium, both Intel and Samsung presented more forward-looking CFET (Complementary Field-Effect Transistor) related data that are closer to mass production requirements.
Intel's paper introduces a CFET inverter built on a (110) crystal orientation silicon substrate. This design integrates a 2×2 array of RibbonFET-style nanosheets at a 45nm gate pitch, combined with PowerVia backside power delivery technology and backside direct contact structure; in addition, the stacked source/drain regions are connected through "epi-to-epi" vias. This design places the PMOS device above the NMOS device — which is opposite to most of the published CFET research solutions. It adopts a hybrid stacked structure that combines silicon materials with (110) and (100) crystal orientations, aiming to improve the hole mobility of the top PMOS device; the two transistors are separated by an intermediate dielectric isolation layer with a thickness of less than 10nm.
Samsung's paper further advances the miniaturization level of CFET and proposes a "3DSFET" structure. This structure adopts three nanosheet channels in both the top and bottom devices, with a gate pitch of 42nm. It is claimed that this is the solution with the largest number of channels among stacked FETs at present. This design is positioned as a highly forward-looking CFET miniaturization solution that is expected to realize industrial mass production in the short term, rather than just a pure research demonstration.
IBM's "Sequential" Solution: "Nanostack"
Although Intel, Samsung and TSMC are mainly focused on monolithic integration, IBM Research has built its CFET (Complementary Field-Effect Transistor) technology roadmap around the "sequential" approach — namely "Nanostack". Instead of forming multiple layers of transistors in the same continuous process flow, this method first fully constructs one layer of transistors, and then builds the next layer above it.
The core consideration for IBM to adopt this solution is the "thermal budget". In a monolithic integration structure, the bottom-layer transistors must withstand all high-temperature steps during the manufacturing process of the upper transistors — according to IBM, the temperature of these annealing processes can exceed 900°C and last for several hours. With the sequential construction method, each layer of transistors is fabricated separately on independent wafers, and then bonded after their respective high-temperature processes are completed, thus avoiding the above thermal limitations.
In addition, IBM's "Nanostack" design does not stack the upper and lower layers of transistors completely vertically aligned, but adopts a staggered layout. IBM says this design allows more direct contacts to be obtained on both the front and back sides of the transistors, which simplifies interconnection wiring — otherwise, the wiring would have to go around the entire height of the stacked structure.
According to IBM's forecasts, this technology can bring about 50% performance improvement, 70% energy efficiency improvement, and 40% area reduction compared with the current 2nm-class process node. IBM also pointed out that the sequential method has stronger scaling potential than a single stacked layer structure: according to its estimates, the circuit area of a four-layer "Nanostack" device can be further reduced by about 40% compared with a two-layer structure. IBM expects that the technology will take about six more years to commercialize from the date of its latest published research results.
Severe Challenges in Manufacturing Processes
Although the specific architectures adopted by various teams are different, they all face a series of similar process challenges when developing CFET (Complementary Field-Effect Transistor). How to connect the bottom-layer transistors located under the top devices — which usually can only be accessed from the backside after wafer thinning — remains one of the most arduous steps in the CFET manufacturing process.
Many of the above papers essentially propose different solutions to this challenge, including: dry etching isolation, staggered layer structure, backside power vias, and epi-to-epi interconnection vias. Another recurring issue is the implementation of high-aspect-ratio structures: when building taller transistor stacks, it is necessary to complete patterning and filling while ensuring that the structure does not collapse. In addition, precise etch selectivity between the top and bottom channel materials is also critical, ensuring that processing one layer of devices does not cause damage to the other layer (Figure 4).
From the perspective of process equipment manufacturers, this technology evolution also presents similar characteristics. Lam Research describes the evolution process from FinFET to GAA (Gate-All-Around) architecture, and then to CFET, as a technical path that increasingly relies on atomic layer etching (ALE) and atomic layer deposition (ALD). Through these processes, spacers and other structural features can be built layer by layer. The company points out that as devices become both taller and smaller in three-dimensional space, the processing must be able to reach deeper and achieve 90-degree right-angle lateral processing.
When Will CFET Be Available?
In various forecasts published over the past three years, the timeline has remained relatively stable, generally pointing to the early 2030s when CFET is expected to be first applied to mass-produced logic chips; depending on the source and the prudence of the definition of "mass production", some forecasts even push it back to 2032. This means that the application of CFET lags behind the current GAA (Gate-All-Around) process by about two full logic node generations. According to the previous development rhythm of the industry, this period of time is sufficient for the "backside power delivery" technology to mature first and become a mainstream feature — in fact, almost all the CFET demonstration cases published so far combine this stacked transistor architecture with some form of backside contacts or backside power delivery wiring.
Compared with when the CFET concept was first proposed, what has changed now is not only the timeline, but also the determination and strength of the industry's investment. At present, four independent institutions, namely Intel, TSMC, Samsung and IBM Research, have successively demonstrated functional circuits based on CFET, rather than just device concepts, at top academic conferences such as IEDM and VLSI Symposium.
In addition, all institutions have clarified their respective integration strategies (three of them adopt monolithic integration, while IBM adopts sequential integration), instead of wavering between multiple technical paths. For a technology that was once regarded as out of reach and only of research value, this sends a clear signal of where cutting-edge logic chip technology will evolve after the miniaturization potential of the GAA (Gate-All-Around) architecture is exhausted.
This article is from the WeChat official account "Semiconductor Industry Watch" (ID: icbank), written by the editorial department, and published with authorization from 36Kr.