MCU, the industry landscape has undergone another major upheaval.

Recently, new changes have emerged in the MCU field. The definition of MCU seems to be evolving again.

On one hand, Synaptics has launched xMCU, which not only integrates CPU, DSP and NPU, but also introduces a high-bandwidth memory architecture similar to HBM, aiming to endow MCU with stronger local AI processing capabilities; on the other hand, manufacturers including Infineon, TI and NXP have started to enhance PQC capabilities by introducing post-quantum cryptography technology into new-generation MCUs. At the same time, NPU is also being deployed in low-cost MCUs, and solutions that allow a single MCU to control multiple motors are also under continuous development.

So what changes are taking place in MCUs? What impact will these new technologies bring to embedded development? Today EEWorld will sort out these trends and related manufacturers.

Is the HBM concept also being introduced into MCUs?

The new Astra SR200 series products released by Synaptics on October 20 are particularly interesting, as it has created a brand new product category called xMCU for itself.

Of course, xMCU is far more than a simple name change. Different from traditional MCUs, it integrates all components into a single chip, endowing the MCU with native AI computing capabilities:

The first is heterogeneous architecture, which takes the lead in adopting the M85+M52 (formerly Arm China "Star" STAR-MC2) combination. Both cores are relatively new, based on the Armv8.1-M architecture, meaning they support Arm Helium technology. The main function of Helium is to perform AI computing, which brings significant performance improvements to DSP and ML applications of small low-power embedded devices, enabling more computationally intensive ML inference algorithms to be deployed at endpoints without a dedicated NPU;

The second is the integrated Synaptics Torq NPU for dedicated neural network processing. As a continuation of Synaptics' joint engineering work with Google on the Coral architecture, Torq NPU delivers 400 GOPS of dedicated neural processing. While raw specification data such as GOPS provides a basic benchmark, the true value of Torq lies in its actual functional capabilities. The integrated accelerator enables the SR200 to perform localized speech recognition directly on the device, including real-time text conversion, multi-object scene classification, spatial segmentation and image recognition. In addition, Synaptics' open-source MLIR/IREE compiler supports industry-standard machine learning frameworks and model formats, which can replace manufacturer-proprietary toolchains, extending the Coral platform's technical accumulation in the field of edge AI to ultra-low-power, always-on IoT applications;

The third aspect is external storage expansion: Synaptics has introduced a custom in-package DRAM interface that works similarly to the high-bandwidth memory (HBM) used in high-end data center chips. Synaptics brings this HBM-like technology to the MCU market, expanding storage capacity to hundreds of MB. This dedicated DRAM data path can transmit massive neural network parameters to the computing cores of the SR200 series at extremely high speeds, allowing the chip to run complex multimodal AI models locally. More importantly, compared with other DRAM solutions on the market, this high-bandwidth memory architecture can reduce storage power consumption by 300% while achieving high-speed data transmission.

According to Synaptics, by integrating Cortex-M85, Cortex-M52, DSP and Torq NPU into a unified architecture, Synaptics enables MCUs to enter the entry-level Linux processor domain without the typical MPU power consumption. In other words, this MCU can also be regarded as a cross-over MCU.

The specific configurations are as follows:

Why did Synaptics develop such a product? Synaptics stated in its blog that edge AI is changing the design challenges of MCUs. When devices need to continuously process visual, voice, audio and sensor data under strict power consumption constraints, simply increasing the CPU operating speed or adding an AI accelerator is far from enough. Processors must be supplied with sufficient data to give full play to their computing power; appropriate computing resources must be awakened at the right time; the entire system must also be able to flexibly switch between microwatt-level monitoring and high-performance inference, while having application processor-level performance and I/O capabilities.

This is exactly the design challenge that Synaptics hopes to solve with the Astra SR200 series xMCU. The Astra SR200 series integrates the design concepts adopted by the SR100 (focused on visual processing) and the SR80 (focused on audio processing), building an architecture natively supporting AI with high-capacity scalable storage capabilities from the bottom up, and supporting organic expansion. The SR200 series consists of multiple product lines developed for different markets and applications.

M33+PQC Becomes a New Competitive Point

PQC (Post-Quantum Cryptography) was very popular some time ago. EEWorld also mentioned this technology in the previous article "The Embedded Industry is Changing: Manufacturers Are Sparing No Effort in PQC Post-Quantum Cryptography". To put it in simple terms, this technology can proactively protect against the potential "harvest now, decrypt later" threat brought by future quantum computing through software upgrades or specially equipped hardware units.

Recently, MCU manufacturers are paying increasing attention to PQC.

On October 19, Infineon expanded its PSOC Control C3 series and launched the PSC3M/P6. This product places special emphasis on Post-Quantum Cryptography (PQC), meets the firmware protection requirements of the U.S. Commercial National Security Algorithm Suite CNSA 2.0, and supports the PSA Level 3 security architecture, helping industrial devices improve firmware security, meet the security challenges in the post-quantum era, and comply with relevant requirements of the EU Cyber Resilience Act (CRA).

In terms of configuration, it adopts the Arm Cortex-M33 core with a maximum main frequency of 180MHz, integrating real-time motor control, power conversion and advanced security functions. A single MCU can control up to four brushless DC motors with or without sensors, which is suitable for industrial drives, drones, smart homes, home appliances, robots, renewable energy, communication servers, data centers, digital medical and other fields.

Integrating fast, high-precision analog processing and digital control capabilities can improve control loop accuracy and system energy efficiency, while supporting wide-bandgap power devices, suitable for high-speed motor control, power factor correction (PFC) and power conversion systems. In addition, the on-chip operational amplifiers, USB and I3C interfaces further expand the application scope of the product.

In addition to the new product, EEWorld also noticed that Infineon recently created a special PQC page that lists all PQC-supported products in detail.

Similarly, EEWorld found that TI recently updated the M33-core mixed-signal MCU MSPM33C321x on its official website, which is TI's first product using the M33 core.

From the Datasheet, EEWorld found that this product supports Post-Quantum Cryptography (PQC) through an efficient software library. In addition, MSPM33C321x also integrates hardware acceleration for AES, SHA and public key cryptographic algorithms (RSA and Elliptic Curve Cryptography ECC), TrustZone technology and Global Security Controller (GSC), as well as integrated immutable Root of Trust (RoT).

The MSPM33C321x MCU provides up to 1MB of embedded Flash program memory and 256KB of SRAM, and is additionally equipped with a 32KB high-durability Flash data storage area for saving application data. All memories integrate Error Correction Code (ECC) across the entire storage space to ensure stable and reliable operation of the device throughout its lifecycle.

The MSPM33C321x MCU also integrates high-performance analog peripherals, including two 12-bit, 9.4MSPS simultaneous sampling Analog-to-Digital Converters (ADC), and two high-speed, low-power comparators. The comparators can cooperate with advanced timers to implement internal fault detection on the chip, or act as external low-power voltage monitors.

NXP has also launched M33+PQC products. On August 18 this year, NXP launched an MCU that integrates 10BASE-T1S, PQC and Rust, and is currently providing sample chips.

In terms of parameters, the Cortex-M33 runs at a maximum of 240MHz, with up to 2MB Flash and 640KB RAM, integrated 10BASE-T1S digital PHY, PQC hardware root of trust, PSA Certified Level 3 security capabilities, and some models support Rust, with interfaces such as USB HS, CAN FD and I3C.

NXP has three very notable features:

First, industrial MCUs start to discover network topologies on their own. MCX A5 can perform topology discovery for nodes in the network, mapping the network composed of industrial sensors and actuators. For a large number of field devices, this can reduce the complexity of installation, debugging and equipment maintenance;

Second, 10BASE-T1S is moving from automotive to industrial edge ends. A single pair of wires can connect multiple nodes, allowing industrial sensors and actuators to directly access the Ethernet network. MCX A5 integrates a digital PHY, but still needs to cooperate with the TJF1410 analog PMD transceiver, which does not mean that the external physical layer device can be completely omitted;

Third, NXP integrates PQC and Rust into the same MCU platform. One solves the long-term cryptographic security problem, and the other solves the software memory security problem. This is more research-worthy than simply adding AES or secure boot functions.

NPU is also being added to M0 MCUs

Adding NPU to MCUs is not a new thing. Products such as STM32N6, PSoC Edge E82 and MAX78000 have already been widely used. However, there is a new trend now, that AI computing is entering the low-cost segment of MCUs.

In March 2026, TI released MSPM0G5187, which adopts 80 MHz Cortex-M0+, integrates TinyEngine NPU, and is equipped with 128 KB Flash and 32 KB SRAM. TI claims that compared with similar accelerator-free MCUs, the latency of specific AI inference tasks can be reduced by up to 90 times, and the energy consumption of a single inference can be reduced by up to 120 times.

Similarly, ROHM announced the Solist-AI solution in 2025, which uses a 48 MHz Cortex-M0+ and self-developed AxlCORE-ODL AI accelerator, targeting device-side anomaly detection. Its feature is not only inference, but also supports the learning and inference of small neural networks on the device side. The official claimed processing speed improvement of about 1000 times is a theoretical comparison value relative to traditional software MCUs.

Single MCU Controls Four Motors Simultaneously

In the past, each motor was configured with one control MCU. Now, a single MCU with stronger performance and richer peripherals can be used for unified management, reducing the number of control chips and PCB area, and lowering the system BOM cost.

As mentioned above, in the PSC3M/P6 series released by Infineon on October 19, the PSC3M6 explicitly supports a single MCU to control up to four brushless motors. It adopts 180 MHz Cortex-M33, integrated high-speed ADC, precision PWM and motor feedback interfaces.

It is worth noting that Infineon places four-motor control in the same product layout as power conversion, robotics, drones and data center power applications.

RX72T is a mature case with public four-motor control demonstration. Its 200 MHz RXv3 core,