Did Kimi Kill EDA? Cadence CEO Finally Responds

Not long ago, Kimi K3 independently designed a chip in 48 hours without using commercial EDA tools such as Cadence and Synopsys. Once the news came out, the market compared it to the impact brought by DeepSeek in 2025, which also reignited the discussion that "AI large models will kill EDA software".

However, at the latest earnings call and Goldman Sachs conference, Cadence CEO Anirudh Devgan continuously responded to this issue. For the extreme scenario where large models directly generate GDSII in the future and complete tapeout by bypassing commercial EDA tools, his answer is: The three-layer framework will continue to exist, and EDA tools will not be commoditized.

01 Can EDA really be replaced?

According to the technical blog of Moonshot AI, this chip has an area of 4 square millimeters, an operating frequency of 100MHz, adopts the public Nangate 45nm open-source standard cell library, and completes a total of 13 modules. The entire process from RTL to tapeout simulation does not use licensed IP or proprietary software of Cadence and Synopsys.

But in Devgan's view, this is a small design using technology from about 20 years ago, and its frequency is 20 to 30 times lower than current technologies. "Even to design one such module, they still need EDA tools."

He said that open-source EDA tools have existed for decades and are used in universities or some professional scenarios, but for "doing real practical design", people still use Cadence.

For the future scenario where powerful large models directly generate GDSII according to chip requirements, send it to the wafer fab for tapeout, and completely bypass commercial EDA tools, Devgan believes that the "ground truth" of physics and mathematics still exists.

At the Goldman Sachs conference on September 9, he further explained why this layer is needed. He stated that AI is essentially a nonlinear fitting, and in complex engineering, AI must be combined with physics. AI can provide more scenarios for optimization, and then the physical layer completes the optimization.

02 Cadence's Answer: Three-Tier Cake

The "three-tier cake" that Cadence has always emphasized is also the core of its AI roadmap. The top layer is AI Agent and orchestration, the middle layer is physical simulation and optimization, and the bottom layer is computing and data.

Devgan said that AI must be "based on physics" in such complex engineering software and engineering processes, and the three layers must be combined. Agents are good at orchestration, planning and optimization, while real navigation and details still need to be completed by the middle layer.

This is also the differentiation that Cadence emphasizes. At the upper layer, Agents require domain knowledge, mental models and knowledge graphs of chip design; the middle layer can call underlying tools through deep APIs, and Cadence has more in-depth engine access; the bottom layer has hardware systems such as Palladium.

At the Goldman Sachs conference, Devgan also introduced Cadence's four current Super Agents, which correspond to front-end design, physical design, analog design, as well as PCB and packaging respectively. According to him, these Agents are tightly integrated with middle-layer tools, and Cadence has 10,000 R&D personnel developing both the upper and middle layers at the same time.

03 The Stronger AI Is, the More EDA Tools Are Called

This is also the core logic of Cadence's response to "AI kills EDA". Devgan said that the significance of Agentic AI is not only to improve the input and output of tools, but to automatically run the design process.

Traditional GenAI can help query documents, but what is really valuable is that Agents can define workflows: execute A, B, C in sequence, and continue to process when encountering problems.

In the past, human designers could usually only conduct three or four experiments at the same time, while Agents can run 100 experiments. Therefore, Agents do not reduce the call of underlying tools, but call more underlying tools.

Cadence has already seen this change. The ChipStack AI Super Agent has more than 20 customer projects and is deployed in multiple chip design production environments; early customer results show that RTL verification speed has increased by more than 40 times, and a typical 5-week verification cycle is shortened to less than one day.

ViraStack has more than 25 customer projects, achieving 2 to 10 times efficiency improvement in analog and custom design. Devgan also said that Cadence's Agentic AI business adopts a new "consumption + subscription" model, while the middle layer continues to adopt the original business model. Customers will not stop purchasing underlying EDA software after buying Agents.

The reason is that the workload of chip design itself is growing exponentially. Devgan recalled that in the past, designing a CPU required 500 people and 5 years, but now it can be completed by 30 to 40 people in 6 months. The design efficiency has increased by about 100 times, but the number of chips and design activities are still increasing.

04 What Is Truly Difficult to Replicate Is the Complete Design System

Therefore, Cadence's competition is not just an AI model.

At present, its EDA products cover digital design, analog, memory, mixed signal, packaging and PCB, and have long-term cooperation with TSMC and Arm, while expanding cooperation with Intel and Samsung.

Devgan said that Cadence has long cooperated with TSMC, and now it has further strengthened its relationship with Intel and Samsung. At the same time, the IP business grew by 30% this year, focusing on key IPs such as SerDes, PCIe, UCIe, HBM, DDR, and continuing to target the low-node and HPC markets.

Hardware is also part of Cadence's system. Devgan said that it is now "impossible" to design complex chips without such hardware systems. Systems such as Palladium can run chips in software environments such as Windows, CUDA, and iOS before the chips come back from the wafer fab, for verification and software development; its custom hardware simulation speed is about 1000 times that of CPU simulation. And this demand is still growing, because the number of chip designs is larger and the scale of chips is getting bigger and bigger.

05 So What Exactly Is EDA Going to Change?

What Cadence is seeing now is not that AI makes EDA disappear, but that the combination of EDA and AI changes the design process. On one end are more and more Agents, and on the other end are still physically accurate tools, computing and data.

Devgan said that customers can of course write their own Agents and let the Agents call Cadence tools, but since Cadence owns both the upper and middle layers and can access internal interfaces and optimization capabilities invisible to users, "many times Cadence can do it more efficiently by itself".

This is also the direction Cadence is pushing forward: to continue higher-level orchestration on top of the four Super Agents, and at the same time to combine Agents more closely with the underlying EDA tools.

For this AI-driven change, Devgan's judgment is very clear: AI will not simply replace EDA, but let AI Agents run more experiments and call more underlying tools to cope with the growing complexity of chip design.

Therefore, what is really worth paying attention to when completing chip design independently in 48 hours may not be "whether EDA will disappear", but that a new design method is taking shape: AI does orchestration at the upper layer, EDA provides physical and mathematical "Ground Truth" at the middle layer, and computing and data provide support at the bottom layer. This is the "three-tier cake" mentioned by Cadence.

This article is from the WeChat official account "Kun Shao Says", author: Kun Shao, published with authorization from 36Kr.