Apple may return to the server market, and the interconnected market has witnessed fierce competition among numerous powerful players vying for market dominance.
Recently, Apple has been reported to be evaluating a return to the commercial server market, with the proposed product targeting AI inference, considering the use of its own M-series chips, and assessing the introduction of NVIDIA's NVLink Fusion interconnect technology.
Apple has previously used self-developed chips for private cloud computing to handle cloud-side tasks for Apple Intelligence. If the company sells servers to external customers, the products will need to be deployed in other enterprises' data centers and integrate with customers' networks, software and operation and maintenance systems. For an enterprise with chip design capabilities, commercial server operation is still a business that requires the organization of external supply chains.
In the following week, interconnect suppliers successively disclosed new progress. On September 23, Cadence announced that it had demonstrated the UALink solution on TSMC's N3P process, providing silicon-verified interface designs for chip companies to adopt open interconnection. On the same day, network chip company Cornelis further introduced its product roadmap for next-generation AI systems, planning to offload part of data processing to network interface cards and switch chips.
When self-developed chips are deployed in servers, enterprises need to decide which interconnection architecture to adopt, and then find partners that can provide interfaces, switching and connection components. The recently disclosed interface verification, product roadmap and sampling plans are all centered around these procurement choices.
01
Switch Market: Replacement and Expansion in Parallel
Statistics released by IDC on September 11 show that in the second quarter of 2026, global data center Ethernet switch market revenue reached 12.3 billion US dollars, a year-on-year increase of 64.5%. This statistic counts switch equipment, covering hyperscale, service provider and enterprise data centers, reflecting that data exchange between servers has formed a considerable scale of procurement demand.
In the same statistics, the proportion of 800GbE products in data center Ethernet switch revenue has risen from 35.9% in the first quarter to 41.2% in the second quarter. While the market size is growing, revenue is also concentrating on products with higher port rates. After the speed of switch ports increases, the supporting switch chips and connection components also need to meet new signal transmission requirements.
A report from Dell'Oro on September 3 pointed out that in the second quarter, the sales of switches for AI back-end networks exceeded that of front-end networks for the first time. The front end undertakes communications such as service access, while the back end is mainly connected to accelerated servers to serve massive data exchange during training and inference processes. Dedicated networks built for computing tasks are changing the network procurement structure of data centers.
In the AI back-end Ethernet segment, 800G equipment has accounted for the vast majority of shipments and revenue in the quarter, and 1.6T products have also started sampling, with shipments expected to expand in the second half of the year. Current procurement and next-generation verification are carried out simultaneously, so suppliers need to ensure the delivery of existing equipment while preparing new products for customers' next round of system design. Whether the R&D schedule aligns with customers' expansion schedule directly determines which round of procurement the products can participate in.
Connecting accelerators and switching equipment also requires cables, optical interconnect components, and chips that recover high-speed signals. Credo sells such products. On September 1, the company announced its latest quarterly results as of August 1, with total revenue reaching 479 million US dollars, a year-on-year increase of 114.7%. These connected products have become a considerable business in the server supply chain.
Credo's products cover copper connections and optical connections, as well as forms such as chips, modules and cables. The type of computing chip used by the server will not eliminate the corresponding connection demand; however, different transmission distances, interfaces and wiring methods used in each generation of system will change the specific component combination. Therefore, independent suppliers need to develop products following customers' complete machine designs, striving for new customers while maintaining the system projects they have already entered.
Dell'Oro predicts that the AI back-end switch market will remain supply-constrained for at least the next one to two years. This creates conditions for manufacturers with delivery capabilities to expand their business, and also makes buyers pay more attention to whether the equipment can be delivered on schedule. Even if a cluster has obtained accelerator cards, it cannot operate at the original intended scale without complete supporting networks; the delivery rhythm of interconnect components needs to be arranged in sync with server procurement.
The institution also judges that current Ethernet sales in the AI back-end mainly come from cross-server and cross-cluster connections, and applications for tighter accelerator interconnection will start to emerge in the second half of the year. The product positions that suppliers can compete for are extending into the racks. What needs to be solved here is not only faster data transmission, but also how accelerators exchange results and collaboratively perform the same task.
02
Self-developed Chips: What Kind of Interconnection Support Is Required
Inside a single server or a group of tightly collaborating accelerators, chips require higher bandwidth and lower-latency connections. The NVLink Fusion that Apple is reported to be evaluating, as well as the UALink verified by Cadence this time, are related to the demands at this level. They determine what kind of interconnection architecture the accelerators adopt, and interface IP, switch chips and connection components are responsible for integrating the corresponding architecture into products.
On September 10, d-Matrix announced that its next-generation Raptor chip will adopt NVLink Fusion, combined with NVIDIA's MGX rack design, and is expected to start shipping in the fourth quarter of 2027. The company focuses its self-development efforts on inference chips, and entrusts part of the interconnection and rack design to existing platforms. For enterprises taking this path, product development needs to align with the platform's interface, system design and verification requirements.
UALink provides another way to organize the supply chain. It is a set of accelerator interconnection standards, and chip design enterprises can adopt interfaces that support this standard, and then cooperate with corresponding switch chips and system manufacturers. The IP provided by Cadence is a pre-designed module that can be integrated into customers' chips; completing silicon verification on the specified process can reduce the work of customers implementing everything from protocol specifications on their own.
This type of interface design is directly related to the manufacturing process. For enterprises preparing for tape-out, whether the standard is open is only one condition, and they also need to check whether there is available IP on the target process, and whether the switch chips can keep up with the complete machine development schedule. The progress Cadence disclosed this time on the N3P process provides specific chip design conditions, which still need to be verified in customers' complete products later.
Once an interface is integrated into chip design, subsequent replacement will involve adjustments to the chip, packaging and board. In this regard, interconnection vendors usually compete for customers earlier than the formal server procurement. Products that participate in the definition and pass verification first are more likely to be included in the bill of materials of this generation of systems; even if other suppliers launch products with similar performance later, they need to re-obtain the customer's design and verification resources.
Complete machine manufacturers are also arranging products for different routes. On September 23, H3C introduced an architecture that adopts UALink inside the cabinet and Ethernet between cabinets at the Yunqi Conference Forum: multiple accelerators are first organized into tightly collaborating computing units, and then these units are connected into a larger cluster. The company also stated that the UniPoD S80000 series will follow up a variety of mainstream interconnection protocols, retaining options for different chip combinations.
The same set of standards can reduce redundant design, but it does not mean that accelerator cards from different manufacturers can be directly mixed and used. H3C mentioned at the meeting that the coexistence of multiple chips and interconnection protocols has increased the cross-vendor adaptation cost. Beyond interfaces, drivers, communication software and fault handling still need to be verified together. As server buyers have more choices, the number of software and hardware combinations that system vendors need to maintain also increases accordingly.
For enterprises preparing to use self-developed chips, accessing existing platforms allows them to reuse the supporting systems that have already been established; adopting open standards and selecting suppliers independently can reserve more combination space while taking on more integration work. Both paths target next-generation server design, and customers need to compare the performance, cost and delivery schedule of the entire solution.
03
Independent Suppliers: Competing for Next-Generation Servers
Cornelis announced a $205 million financing on September 14, with the funds to be used for product expansion, production and customer deployment. The company's existing network technology has been used in hundreds of data centers. At that time, CN5000 was in shipment, and CN6000 had been sampled to customers, with expanded supply expected in the fourth quarter. To enter the in-rack interconnection market, the company needs to continue developing new products based on this business foundation.
According to the roadmap further disclosed on September 23, Cornelis' next-generation CN7000 plans to support UALink and other interconnection standards, providing a combination of network interface cards and switch chips. Its role is to provide the hardware and software that implement interconnection. After customers adopt open standards, they still need to purchase such products to connect the accelerators.
The selling point Cornelis adds to this set of products is to let network equipment undertake part of the data processing. For example, when multiple accelerators jointly train a model, the results calculated by each need to be aggregated and then distributed; if the network interface card and switch chip can complete part of the aggregation while the data passes through, it can reduce the repeated sending, receiving and processing work on the accelerator side. The company also plans to support inference cache migration to reduce the overhead of host involvement in communication.
The company refers to these functions as the Active Compute Fabric, and plans to configure programmable processing cores so that some new operations can be added via firmware updates. For customers, the value lies in reducing the time that already purchased accelerators spend waiting for data. The specific benefits depend on tasks and system configurations, and the utilization improvements currently announced by Cornelis are mainly derived from model calculations.
According to its latest schedule, the CN7000 that fully implements this roadmap is targeted for customer deployment in 2028. This generation of network interface cards is planned to work on standard Ethernet networks, and additional functions can be added when paired with the company's own switch chips. Customers can therefore verify the network interface cards first, and then evaluate whether to adopt more supporting products after confirming the benefits. Cornelis' accumulated customer relationships in the past can provide access to projects, but the new architecture still needs to go through its own onboarding process.
Delos Data chooses to enter the market from the interface for accelerators to access the network. The Data Interface it released on September 15 comes in three forms: chiplet, near-packaged optical component and board, targeting accelerators as well as devices such as CPUs and memory. It also needs to align with the interconnection protocols and systems selected by customers, focusing on coordinating data exchange between different devices and handling part of the faults at the interface.
The three forms correspond to different cooperation stages. Chiplets need to participate in the design and packaging of next-generation accelerators, while boards provide access methods on the system side. Therefore, Delos needs to target both chip design enterprises and customers that build servers and clusters; whether it can be included in projects depends on when customers finalize the chip, packaging and network solutions.
As the number of accelerators increases, a fault in one chip or link may cause other devices to wait for data. Delos hopes that the hardware interface can detect faults and manage recovery to reduce the impact on the entire task. At present, its cluster platform has been used in existing infrastructure, and new server products are planned to be sampled by the end of 2026.
In this release, Delos also added pre-deployment design and simulation tools to the cluster platform. Customers can use PCIe cards to verify real workloads, test interfaces through pre-tapeout simulation, and compare different connection methods and fault scenarios in cluster-level models. This allows chip design, network layout and software tasks to be evaluated in advance, so that customers can identify adaptation issues in the solution before deciding on construction.
Delos also disclosed more than $100 million in financing on the same day, clarifying that the funds will be used to expand its software and hardware engineering teams, product development and sales. Verification tools are also part of the products it provides to customers. For such enterprises, R&D investment needs to cover software and system support beyond interface chips, and customer onboarding work will continue through the testing, deployment and operation phases.
On September 21, Qualcomm, Lumentum and Corning announced a joint demonstration plan for optical inter-chip connections, hoping to extend high-density connections to tens of meters through optical fibers. In this solution, Qualcomm provides the inter-chip interface subsystem, Lumentum provides the optical engine, and Corning provides the fiber optic connection. The electrical interface on the chip side and the subsequent optical signal transmission need to be designed together. This combination targets future near-packaged and co-packaged optical systems, and is still in the proof-of-concept stage.
Buyers are also controlling the complexity of combinations. Natalie Serrino, co-founder of inference infrastructure company Gimlet Labs, said in an interview published on September 21 that the company hopes to adopt two to four types of chips in one data center, and find combinations that can be deployed repeatedly. Different chips can undertake their respective good at computing tasks, but increasing the types of chips will also increase connection and software adaptation work.
04
Conclusion
It remains to be confirmed whether Apple will return to the commercial server market. The interconnection market is expanding, and suppliers' products are still at different stages. Going forward, whether products can pass customer verification, operate stably with different chips and be delivered on schedule will affect the order acquisition and deployment expansion progress of these enterprises.
This article is from the WeChat public account "Semiconductor Industry Insight" (ID: ICViews), written by Jun Xi, republished with authorization from 36Kr.