The world's first chip completely designed by AI

A few days ago, Architect Labs, a custom silicon AI research lab led by Ebrahim Hussain and Aaditya Subedi, announced that its AI system has generated and fully verified Redwood, an end-to-end production-ready AI accelerator, based on human-written specifications.

With only two human architects providing technical specifications, the AI system completed the chip design and full verification in less than two weeks. It also participated in the design of firmware and custom kernels, and mapped modern AI models to hardware. The final accelerator currently runs on the FPGA platform to perform inference on multi-billion-parameter models including Llama and Qwen.

According to relevant sources, Redwood represents a significant milestone in the semiconductor industry: an AI system has autonomously designed a mass-producible AI chip that can run AI models. This approach creates a feedback loop between AI models and the hardware optimized for them, which is expected to accelerate chip design speed far beyond the traditional development cycle.

Performance test results also show that Redwood is far more than a proof of concept. Based on Samsung's 8nm process, Redwood delivers 1.75x the throughput of NVIDIA Jetson Orin Nano while reducing power consumption by 1.9x, which means its performance per watt is improved by 3.4x for the same AI model.

Chip design can take years and cost hundreds of millions of dollars, and the growing shortage of skilled professionals has concentrated advanced semiconductor R&D in the hands of a few large companies. As a result, AI workloads often need to be adapted to hardware designed long before the latest models are released.

Redwood takes a different approach, co-designing hardware and software from the very beginning. Kernels, firmware and RTL code are developed and optimized together, enabling the chip to be customized for AI workloads instead of forcing software to adapt to existing hardware.

This creates a continuous feedback loop where improved AI models can inform better hardware design, and more efficient hardware can deliver better AI performance, potentially accelerating both ends of the development cycle.

"When I started in this industry 40 years ago, chip design only required one or two engineers. Since then, design complexity, time consumption and risk have all grown exponentially. Even with continuous advancements in EDA tools and technologies, a single chip project still takes years of work and a huge engineering team," said Sunil Shenoy, former Senior Vice President of Engineering at Intel. "Redwood has truly delivered a paradigm shift and set a new benchmark for the technological frontier. Architect Labs is democratizing capabilities that were once only accessible to a few giants at a speed I could not have imagined before. Their approach promises to bring hardware back to the future."

Inside Redwood: The Cutting-Edge AI Accelerator

Redwood is an end-to-end AI inference platform designed for physical AI applications that require real-time performance under strict power constraints, such as robots, drones and edge devices.

At its core is a scalable grid of matrix and vector computing engines connected by a dedicated Network-on-Chip. The complete AI inference pipeline, including attention mechanisms, key-value caching and just-in-time quantization, runs directly on the chip without relying on a host processor.

The computing engines, network, firmware and custom kernels are designed and optimized as a unified system, allowing the hardware to closely match modern AI workloads. Redwood can also be scaled up to larger data center SoCs, or operate as a standalone chipset.

Key statistics about the autonomous Redwood design:

Autonomous design and verification: 100% of the RTL, UVM verification environment, formal verification, firmware, drivers and custom computing kernels are end-to-end generated by Architect Labs' AI system based on human-written specifications in less than two weeks, with the project involving only two human architects.

Signoff-level verification standards with zero hardware defects: The code and functional coverage of each module from a single IP to the entire SoC exceed 95%. The verification process uses commercial EDA tools, Architect Labs' proprietary formal verification engine, and hardware-in-the-loop verification. No defects were found in the first batch of RTL code from simulation to FPGA platform.

Run real AI models on real hardware: Redwood Nano is deployed on AMD Versal FPGA, running at 250MHz, and can perform real-time single-batch inference on open-weight models including Qwen. Architect Labs conducted a live hardware demo at this year's Design Automation Conference (DAC), and was one of the few companies at the show that could demonstrate an AI-designed accelerator and run model inference in real time.

Surpass today's leading AI chips: On the Samsung 8nm process platform, the same process node used by NVIDIA Jetson Orin Nano, Redwood delivers 1.75x higher throughput, 1.9x lower power consumption, and 3.4x higher performance per watt (benchmarked against Jetson running the same model). These projections are based on direct measurements from FPGAs, not simulations alone.

Architecture iterations take days instead of quarters: Any change to the high-level specification results in full regeneration, re-verification and re-deployment of the hardware within 48 hours, except for SoC-level runs limited by EDA tool runtime.

Recursive self-improvement: The AI models deployed on Redwood are exposed as API endpoints, which discover timing and kernel optimizations for the accelerator itself at almost zero inference cost, closing the loop between AI and the silicon that drives it.

"Every advancement in the computing era relies on underlying hardware, but is also limited by who has the ability to manufacture the corresponding chips," said Steve Jang, Founder and Managing Partner of Kindred Ventures. "The advent of the Redwood chip is an initial proof that this barrier can be broken: two people - starting from a written specification and target AI model - using Architect Labs' system, completed the design, verification and deployment of a highly competitive AI accelerator in just a few weeks. Whether you are a cutting-edge research lab, a robot manufacturer or a cloud operator, the concept of customizing chips for your product or platform is gradually becoming a reality today."

A Fundamentally Innovative Approach to Silicon Software Design

Architect Labs' AI system can optimize the entire computing stack in parallel, from models and kernels to firmware and RTL code, instead of following the sequential, isolated workflows common in traditional chip design. This allows software and chips to be co-optimized during the tape-out process, potentially reducing design iteration time from months to weeks.

This approach can shift functions between software and hardware based on efficiency, for example, replacing thousands of software cycles with dedicated hardware logic, or moving scheduling tasks to the compiler. Redwood proves that these trade-offs can now be designed, verified and tested in hardware within days, laying the foundation for scaling this approach to more complex chips.

"Thirty years ago, foundries like TSMC enabled anyone with a design to access world-class manufacturing capabilities, which spawned the fabless semiconductor industry represented by companies such as NVIDIA, Broadcom and Apple," said Ebrahim Hussain, Co-Founder and CEO of Architect Labs. "Similarly, we are leading the development of the 'fabless design' semiconductor industry, where chips like Redwood can be co-designed and evolved with the running workloads. We envision that software companies with intensive workloads or dedicated AI models can access co-designed custom chips without building a huge design team, investing a decade in architecture, or settling for off-the-shelf general-purpose solutions, thus saving performance, power and cost. Every important workload deserves its own custom chip. We are building that future."

Architect Labs stated that the company has applied the same approach to Fortune 500 partners to co-design custom chips at the speed of software development, compressing programs that originally took months to run into completion within weeks. Redwood is the first public demonstration of the results of this technology.

Full Paper Translation Attached:

Modern AI workloads and the hardware required to run them evolve on different timescales: architecture definitions are made years before production chips, while target workloads change on a monthly basis. As a result, design decisions are made under high uncertainty, and double penalties are paid: once for the added generality to mitigate risk, and again when new workloads are difficult to map onto frozen chips.

With Moore's Law stalling, specialization has become the main source of performance per watt, and requires design cycles to keep pace with the rhythm of workloads. We propose an end-to-end AI system that simplifies the entire stack from software to chips into a single optimization loop, where hardware and software are co-designed and verified under the same objective. The first demonstration of this system is Redwood, a cutting-edge AI accelerator built for single-batch, low-power, ultra-low-latency inference for physical AI. Based on high-level specifications provided by two human architects, the system autonomously generated performance models, RTL designs, UVM environments, formal proofs, firmware and kernels in less than two weeks, with no human intervention below the specification level.

With commercial EDA tools, our self-developed formal engine, and hardware-in-the-loop verification, we achieved 95% coverage for each module. Specification changes are re-verified and deployed to hardware within 48 hours. Redwood Nano, its ultra-low-power FPGA variant, can run multi-billion-parameter models such as Llama and Qwen. On Samsung 8nm process (the same process node as Jetson Orin Nano), Redwood delivers 1.75x higher throughput, 1.9x lower power consumption, and 3.4x higher performance per watt compared to the Jetson benchmark measured on the same model.

Qwen running on Redwood also contributes to the design of the next-generation Redwood, an early step toward recursive self-improvement. To the best of our knowledge, this is the first production-ready AI accelerator designed end-to-end by an AI system and capable of running modern AI models.

1. Introduction

The EDA industry currently reports that artificial intelligence (AI) has brought order-of-magnitude improvements in RTL generation, verification, debugging and exploration, including reducing months of work to days and achieving up to 10x productivity gains in design and verification workflows. However, only 14% of IC/ASIC projects achieve first-silicon success, the lowest level in nearly two decades, while 75% of projects fall behind schedule, as chip projects face increasingly complex design challenges arising from heterogeneous integration, physical effects at advanced nodes, and increasingly strict power, performance and area (PPA) constraints. This discrepancy highlights a serious mismatch between task-level productivity claims and overall project outcomes: AI accelerates individual activities, but has not yet demonstrated clear end-to-end project improvements on increasingly complex SoCs.

At the same time, publicly demonstrated end-to-end AI-generated designs remain limited to simple examples, such as toy RISC-V cores or enhanced numerical data paths. Few of these technologies have been verified on physical hardware, which is the ultimate constraint for hardware design. We argue that the opportunity for AI in hardware design lies not in accelerating tasks within existing processes, but in reimagining the entire process itself. When architectures, RTL, verification, firmware and kernels are all generated from a single specification and optimized for the same objective, the sequential handoff links that cause project delays disappear, and hardware-software co-design becomes a property of the system itself, rather than a coordination process between teams.

To address this, we introduce Redwood, a cutting-edge AI accelerator that is end-to-end designed, verified, programmed and deployed by the system. Two architects documented workload and architecture constraints in a high-level specification. Based on this specification, the system autonomously generated performance models, RTL code, UVM environments, formal proofs, firmware, drivers and custom computing kernels. In less than two weeks, the system completed the full design from scratch, achieving 95% code and functional coverage for each module, and deployed the Redwood Nano configuration on AMD Versal FPGA. In the third week, Qwen3-0.6B inference went online. During this period, every architecture change was regenerated, re-verified and re-deployed to hardware within 48 hours. Redwood Nano is evaluated on a Samsung 8nm-class process similar to that of NVIDIA Jetson Orin Nano, and is projected to deliver 1.75x higher decoding throughput, 1.9x lower power consumption, and 3.4x higher performance per watt (compared to the Jetson benchmark running the same model).

2. Architecture

Redwood is a tile-based spatial dataflow accelerator that uses a standard AXI4 memory-mapped interface: AXI-Lite for control and configuration, and wide AXI4 with full burst support for bulk data transfer (Figure 1). A dedicated DMA engine is responsible for all data transfer with external DRAM. The Global DMA (GDMA) architecture performs bulk memory-to-memory transfers between external memory and three last-level SRAM banks (LLC) on the west, north and east sides of the chip, while edge DMA engines handle data staging across the compute fabric. The global control region is responsible for sequencing the accelerator and contains a global control core (MCU), a global task manager, and a 48-bit global timer (HAC) that broadcasts to each tile for time-isolated scheduling. This region is responsible for launching, coordinating and tearing down kernels such as FlashAttention and GEMM/GEMV. Since memory interfaces are limited to modular DMA engines, Redwood can be integrated into larger SoCs or packaged as a standalone chip. The DMA backend can be redirected from AXI4 to protocols such as ACE and CHI without affecting the compute fabric.

The compute fabric is an N × M grid of identical tiles, surrounded by edge DMA engines. Each tile contains a RISC-V-based tile control core (CRV) and a compute engine specifically designed for Transformer inference. The matrix engine (CMXM) provides systolic GEMM and matrix-vector (GEMV) data paths, and streams data directly to the vector engine (CVXM), which provides SIMD, transpose and floating-point activation units. Large partitioned scratchpads minimize data movement within Redwood. The compute engines are co-designed with kernel software, so they can directly map to key Transformer operators — attention, GEMM, normalization and activation — and execute kernels such as FlashAttention and GEMM as hardware-scheduled tasks rather than general-purpose instruction streams. A high-bandwidth, internally designed, credit-based Network-on-Chip (NoC) carries tile-to-tile, DMA-to-tile and tile-to-DMA traffic. It provides low-overhead broadcast and multicast, table-based flow redirection, and per-link flow control.

A. Tile Architecture

Each tile in the Redwood architecture is divided into a Front End (FE) and a Back End (BE), as shown in Figure 2. The FE is responsible for control and programming, while the BE handles data transfer and computation. Separating sparse control from high-bandwidth data processing allows the FE to run at a lower clock frequency, and in some cases the FE can be powered down during kernel execution, resulting in significant power savings. Kernel software runs on the tile control core (CRV), while the Core Task Manager (CTM) connects the CRV to BE functional units and coordinates tasks across multiple configurable units.

The hardware units inside the Tile BE are co-designed for modern Transformer workloads, including device-side prefill and decoding. Compute units include GEMV and GEMM engines for matrix operations (built from an array of integer-based multiply-accumulate (MAC) units), and multi-channel SIMD engines for element-wise operations (built from an array of floating-point units (FPUs)), capable of handling reductions, lookup table (LUT)-based operations and more (Figure 3). One optimization adopts the analog softmax algorithm from FlashAttention-4, which reuses existing SIMD resources to perform operations that would otherwise occupy a large silicon area. These functional units and the CRV share access to a local 512 KB core memory (CMEM) via a high-bandwidth bus. Local ingress and egress DMA engines are responsible for moving data in and out of CMEM.

B. Control Mechanism

To perform computation with a Redwood tile,