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Led by Professor Sun Qi from Zhejiang University, Xinliu Weilan has closed its first round of financing.

投资界2026-09-01 17:53
AI for Chip Design

It is learned from PEdaily AI that Hangzhou Xinliu Weilan Intelligent Technology Co., Ltd. (referred to as "Xinliu Weilan"), an innovative enterprise specializing in AI for IC design, has announced the completion of its first round of financing of tens of millions of RMB, which is exclusively invested by Qigao Capital.

Nowadays, the complexity of chip design is getting increasingly higher, and the original human input can no longer support related work. Against this backdrop, Sun Qi, a researcher at Zhejiang University, led the team to found Xinliu Weilan in 2026, combining AI with electronic design automation experience, aiming to build a new-generation intelligent platform for chip design.

Up to now, Xinliu Weilan has become one of the few teams in the industry that have truly got through the industrial-grade EDA tool chain and deployed Agents in advanced process chip projects. Its long-term vision has been clear: "Design AI with AI."

Designing Chips with AI: A Team from Zhejiang University Just Completed Financing

Sun Qi, founder of Xinliu Weilan, is currently a researcher and doctoral supervisor at Zhejiang University, once a postdoctoral fellow at Cornell University. He has long been deeply engaged in the AI+IC field, published nearly a hundred papers in top international conferences and journals, and his achievements have won the first prize of Zhejiang Provincial Science and Technology Progress Award, Huawei Spark Award, EDA Youth Science and Technology Award, and 8 Best Paper Awards/Nominations of international academic conferences.

Dr. Chen Zhengrui, the technical director, took the lead in proposing the Agentic EDA infrastructure oriented to the real industrial tool chain. He has delivered mass-production level standard cell libraries and back-end optimization solutions for mainstream IDM enterprises, with rich experience in tape-out and industrial implementation. In addition, the project has also received high recognition from Academician Wu Hanming, Dean of the Faculty of Information of Zhejiang University, and Professor Zhuo Cheng, Vice Dean of the College of Integrated Circuits. As strategic consultants and senior industry leaders of Xinliu Weilan, the two experts will provide high-level strategic guidance and support for Xinliu Weilan from technical route planning, industrial resource docking to enterprise-level implementation.

EDA, namely Electronic Design Automation, is the most upstream infrastructure in the chip industry chain. By using computer software to complete the processes of integrated circuit design, simulation and verification, it is a key factor that determines the performance, yield and R&D cycle of chips.

The emergence of AI Agent makes it possible to improve the engineering practice capability of the whole field. What Sun Qi and his team have long focused on is how to make algorithms enter the real tool flow, and how to verify judgments with verifiable engineering results?

Therefore, with Generalized AI for Design as the vision, Xinliu Weilan came into being in 2026. It aims to develop AI-driven EDA tools, lower the threshold of chip design, shorten the R&D cycle, enable more innovative chips to move from conception to mass production, and promote the independent and controllable development of China's semiconductor industry.

Xinliu Weilan has built an intelligent IC design platform that can understand design objectives, plan processes, orchestrate tools, analyze results and continuously iterate and optimize. After engineers set objectives and constraints, the agent can complete task decomposition, call industrial tools to execute design, interpret report data, and independently decide the next round of optimization actions.

Specifically, focusing on the two core issues of "how to observe" and "how to continuously promote the work", Xinliu Weilan has launched a product consisting of two parts: proprietary vertical domain model and agent engineering framework

On the model side, the team has a self-developed large IC design model Wavelet, which is responsible for professional understanding and reasoning in chip engineering. The model can understand professional contexts such as netlist, layout and routing, timing, power consumption, and has the VLSI advanced process data processing capability.

On the process side, Xinliu Weilan has built a highly stable, quality-controllable engineering-level long-process control system. Its Orbit supports long-term stable operation, anomaly diagnosis and strategy adjustment of cross-tool and cross-stage tasks, and can continuously learn from chip design projects, precipitating the tacit experience of senior engineers into reusable capabilities.

Different from similar projects that only stay at the stage of tool invocation or concept verification, Xinliu Weilan adopts a real industrial tool chain. By going deep into the real industrial site, systematically combining models, data, tool chains, process control and chip engineering experience, it realizes more reliable engineering-level AI empowerment.

At present, Xinliu Weilan's system has got through the whole physical design process in real projects below 10nm with a scale of nearly 10 million gates, and continuously optimizes PPA (Performance, Power, Area), realizing long-term stable and high-quality operation. Meanwhile, it supports optimization of advanced devices such as GAA, as well as microarchitecture optimization of ultra-high-dimensional industrial processors.

AI for Chip Design

This may be the dream time for chip designers.

In the past decades, EDA software has become more and more powerful, the scale of chips has been larger and larger, and the design process has become more and more automated. However, at the critical stage that determines whether the project can converge on schedule, a large number of engineers can only be invested through the manpower-intensive approach to fix various violations, making the link difficult and costly.

The reason is very simple: even with almost unlimited server resources and tool licenses, a large number of convergence strategies can be tried in parallel, the project still needs to carry out a lot of work including report interpretation, root cause location, modification and verification — these works still highly rely on the professional judgment of senior engineers.

In other words, the complexity of chips can continue to expand, while the engineering practice capability can hardly grow at the same speed, and the two no longer have a linear supporting relationship.

Facing this problem, AI agents are just tailor-made solutions: there are a large number of iterative works in the design process, and the optimization path varies from project to project, but the effect of each step can be verified through clear engineering indicators. The corresponding agent workflow is to first understand the current design state, analyze the source of the problem, determine the next step strategy, call real EDA tools for execution, judge whether the effect is valid according to the new result, and proceed to the next round.

In other words, enterprises need to first build a system that can carry complex engineering processes in the high-constraint scenario of chips, connecting design objectives, domain knowledge, professional tools, process status and verification feedback into a traceable engineering closed loop.

This entry point is small enough but sufficiently "heavy". As Dr. Zhang Yong, Founding Managing Partner of Qigao Capital, said: "Chip design is moving from tool automation to process intelligence centered on large models and agents, and the compound threshold in this direction is very high. The Xinliu Weilan team has long-term academic accumulation, industrial delivery experience and real scenario verification capabilities. We are optimistic about the long-term reconstruction of the chip R&D paradigm brought by Agentic EDA, and we also expect Xinliu Weilan to grow into an important infrastructure enterprise in the global IC agent field."

What is more promising is that such an engineering architecture also expands new space for the design ideas of complex systems.

In summary, chip design is just a branch of human complex engineering. In more complex systems, engineers also need to face changing states, conflicting constraints, scattered professional tools, and verification processes that cannot be replaced by one-time generation. The real bottleneck of the system is often not the lack of a better answer, but the lack of an engineering practice capability that can continuously understand objectives, enter the environment, execute tasks and correct itself according to feedback.

After all, model capabilities can change rapidly, but the knowledge, processes, feedback and responsibilities in complex engineering must be precipitated layer by layer — these parts are often more difficult to replicate.

This is also why Xinliu Weilan takes "Generalized AI for Design" as its long-term anchor. Starting from the specific scenario of chip design, it builds a general-purpose intelligent design operating system oriented to complex system design. The so-called "general purpose" means that the design objectives, professional knowledge, engineering tools, operation status and verification mechanisms scattered in different fields can be organized into a reusable agent engineering architecture.

"We hope to build a truly usable and credible IC agent system for design engineers, which can not only amplify the efficiency of engineers by dozens of times, but also precipitate the experience accumulated by enterprises for many years into the system, so that the scarce experience of senior engineers will no longer become the bottleneck of complex projects, and elevate the value of human beings from Implementation to Innovation." Sun Qi said.

Beyond chips, the blueprint carrying the broad design wisdom of human beings is unfolding slowly.

This article is from the WeChat Official Account "PEdaily AI", author: Yu Mengying, published with authorization from 36Kr.