Just now, Xiaomi released its full lineup of AI chips, and Lei Jun revealed a hidden Easter egg: the chips are very expensive, do not disassemble them.

Next month, Apple will launch the iPhone 18 Pro series and its first foldable iPhone. Unexpectedly, on the eve of this much-anticipated "tech gala", Xiaomi has completely upended the game.

At the just-concluded Xuanjie Technology Communication Conference, Xiaomi's second-generation self-developed SoC "Xuanjie O3" has refreshed the mobile SoC benchmark record: its Geekbench 6.5 multi-core score has reached 15,000 points, nearly 40% higher than Apple A19 Pro, the current industry performance benchmark. Its extreme AnTuTu score in a low-temperature laboratory environment even exceeded the 5 million mark, reaching 5.22 million points.

But this 5.22 million score is far from the highlight of this conference.

Lei Jun also unveiled a hidden Easter egg embedded in Xuanjie O3: when you magnify the interior of the Xuanjie O3 chip under a microscope, you can see a tiny OK gesture that is only 60 micrometers in size.

This Easter egg implies "everything is OK", but Lei Jun does not recommend that people disassemble the chip, as this chip is quite expensive.

Ten full large cores: both powerful and power-efficient

To achieve such a staggering theoretical performance, Xiaomi has equipped Xuanjie O3 with a very aggressive 10-core CPU configuration, consisting of 6 super-large cores paired with 4 large cores, with a maximum main frequency of 4.35GHz. Compared with the simple pursuit of an extremely high single-core main frequency, O3 obviously puts more emphasis on the multi-core concurrent throughput capacity.

To fit as many as 10 full large cores in a mobile SoC where every square millimeter of space is precious, sufficient physical space is required first. Under the same advanced 3nm process, the chip area of O3 has expanded from 109mm² of the previous generation to 133mm², and the number of transistors has also increased from 19 billion to 24 billion (26% higher than that of O1), with the overall size of the silicon wafer increased significantly. O3's leading advantage in multi-core performance is largely derived from the parallel efficiency of this 10-core full large-core architecture.

The flip side of the full large-core architecture is that power consumption and heat generation are harder to control. Mobile phones are mostly used for light-load scenarios such as watching videos, replying to messages, and browsing web pages. If these large cores cannot reduce their performance in time, even the most impressive scores will easily turn into a burden on battery life and temperature. Therefore, in addition to emphasizing performance, Xiaomi also highlighted that in 80% of the daily medium and low load scenarios, O3's power consumption is 25% lower than that of the previous generation.

Photo | Official Xiaomi

In addition to the CPU, the GPU has also achieved substantial improvements this time. Xuanjie O3 is equipped with a 16-core G2-Ultra NX. According to official data, its graphics performance is 85% higher than that of the previous generation, and its ray tracing performance is 182% higher. The GPU also integrates 8 NX neural processing units to deliver 36 TOPS of computing power for game super-resolution and frame interpolation.

More importantly, at the same performance level, O3's power consumption is up to 64% lower than that of O1. High performance can be maintained for a longer time, and heat generation and power drain are easier to control.

In addition to computing and graphics, imaging is also a key upgrade for O3. This chip integrates Xiaomi's 5th-generation flagship ISP architecture, supports a maximum 432-megapixel single camera and 24-bit maximum bit width, and has the capability of concurrent processing for 64M+64M+50M triple cameras. Combined with the hardware-level intelligent imaging engine, it integrates 4K 60FPS AINR (AI Noise Reduction) night video into the underlying chip, leaving sufficient redundancy for the computational photography of subsequent flagship models.

The chip runs so fast that the memory can hardly keep up

However, when the computing power of CPU, GPU and NPU is fully unleashed, chip designers will soon hit another invisible wall: the speed of data transfer can no longer keep up.

This is like a top-tier kitchen with more and more chefs who can chop ingredients and stir-fry at lightning speed. But if the passage for delivering ingredients is narrow, or the ingredient warehouse is too far from the stove, the chefs can only stand in front of the stove with empty pans waiting after finishing one dish. If the computing power is blocked in the memory channel, even the most impressive scores cannot bring a smooth user experience.

To widen the passage for these "chefs", O3 has also made great efforts in the memory system. It is the first in the industry to support 4×24bit bit width and 10667Mbps LPDDR6 memory, directly pushing the bandwidth to 113.8GB/s, nearly 50% higher than the mainstream LPDDR5X.

At the same time, the total main cache inside the chip has been expanded to about 60MB (including 12MB CPU L2, 16MB L3 and 16MB system-level cache SLC), which is equivalent to placing the most commonly used ingredients neatly right next to the stove.

Combined with the reconstructed self-developed unified fusion bus and high-level physical wiring, O3's static memory access latency is compressed to 82ns (dynamic latency with background load is 177ns), which is faster than Apple A19 Pro's 92ns/211ns and the previous generation O1's 121ns/384ns.

This hunger for high bandwidth and low latency is multiplied in edge-side AI scenarios. Every time a large model outputs a token, essentially, it needs to read the model weights of billions of parameters completely from the memory.

200 TOPS of A8W4 tensor computing power and 3.13 TFLOPS of vector computing power are not enough. O3 is specially equipped with hardware Huffman lossless compression technology for the customized Xiaomi MiMo 5-value quantization model, which directly saves 30% of memory bandwidth occupation. Combined with 28MB NPU near-memory, according to official laboratory data, the first word response speed of MiMo 3B is increased by 40%, the inference speed is increased by 45%, and the operating power consumption is reduced by 26%.

In the general-purpose SoC for mobile phones that needs to take all aspects into account, Xiaomi has basically maxed out all possible optimizations. But if we break away from the constraints of mobile phones and build a chip dedicated to running large models, how should we solve this data bottleneck?

When the communication conference was coming to an end, Xiaomi presented its One More Thing — Xuanjie O100.

Xuanjie O100: High-bandwidth AI acceleration chip

Different from general-purpose SoCs that take into account daily multi-tasking, O100 is a high-bandwidth AI acceleration chip fully oriented to large model inference. Although its logic process uses the relatively mature 6nm, its packaging method is more radical:

Xiaomi adopts Wafer on Wafer wafer-level 3D stacking and Hybrid Bonding technology, directly bonding and stacking two layers of high-speed AI-specific DRAM wafers and one layer of high-performance NPU wafer in the vertical direction, turning the originally planar data path into a "vertical through" structure.

Through the innovative Face to Face metal layer direct connection structure, the two layers of wafers are connected by 2.58 million physical bonding nodes. The TSV silicon via aperture is only 0.7μm, and the bonding pitch is reduced to 1.4μm.

The micrometer-scale physical interconnection distance allows data to flow at high speed between the computing core and the dedicated memory through an extremely short path, directly pushing O100's memory bandwidth to an astonishing 1.22TB/s — 16 times that of the current mainstream flagship mobile phone LPDDR5X.

To fully utilize this amazing bandwidth throughput, O100 also designs different interconnection architectures for its 14 NPU cores: the Prefill stage for processing long prompts uses a Ring network for step-by-step transmission, while the Decode stage for outputting words one by one switches to an All-to-All broadcast network to enable instant synchronization of multiple cores.

In Xiaomi's lab tests, O100 paired with Xiaomi MiMo achieved an ultra-high-speed local inference result of up to 330Tokens/s.

From O3 to O100, Xiaomi has actually been solving the same problem: as computing power becomes stronger and stronger, how to prevent data from being "blocked" on the path. This applies to mobile phones, as well as large models. When this line of thinking is extended to larger terminals, the next stop is automobiles.

Xiaomi is building a full set of chips for its own AI

Xuanjie D100: High-computing-power AI chip for intelligent driving

The Xuanjie D100 for intelligent driving scenarios adopts the advanced 3nm process, is equipped with a 20-core CPU and a 16-core NPU. Its most impressive indicator is that it supports a maximum of 160GB of unified memory. The official confirmed that it has successfully deployed a 200B parameter scale model locally, and plans to officially launch it for commercial use next year.