Everyone wants a piece of Broadcom's business.

Recently, citing market rumors from SemiAnalysis, it is reported that Google is collaborating with AMD to develop projects related to the 10th generation TPU. If the project is finally implemented, it will not only be a significant step for AMD to truly enter the large-scale data center AI ASIC market, but also reflect an increasingly obvious industrial trend: Custom chips are becoming a new must-contest battlefield in the AI era.

In fact, not only AMD, but many major chip manufacturers including Intel and MediaTek have been accelerating their move into the "Custom Silicon" track across boundaries in recent years.

This was originally the business that Broadcom and Marvell are best at.

Over the past decade or more, they have verified a mature and highly attractive business model: cloud computing giants such as Google and Amazon can master their own workloads, chip architectures and even some core IP, without having to build a complete chip team covering physical design, high-speed interfaces, advanced packaging, verification, mass production and even supply chain management on their own. By cooperating with ASIC manufacturers, these cloud vendors can turn the chip architectures defined for their own businesses into products that can be mass-produced on a large scale and run stably in data centers.

Previously, this was still a relatively low-key business. But the outbreak of AI has completely changed its scale and importance. Taking Broadcom as an example, its revenue from AI semiconductors in the second quarter of fiscal 2026 reached as high as 10.8 billion US dollars, a year-on-year surge of 143%, and the growth momentum comes from custom AI accelerators and AI network chips.

Facing this hundred-billion-dollar market, the competition among giants around custom chips has only just begun.

ASIC has become a "must-have option" for AI giants

In the past few years, with the outbreak of large model training demands, GPUs have almost become synonymous with AI computing power. The most concerned issue in the whole industry has always been: who can challenge NVIDIA?

However, beyond GPUs, another market with an increasingly large scale has actually taken shape quietly. Google TPU, AWS Trainium, Meta MTIA, and more and more AI chips independently defined by Hyperscalers all illustrate one thing: when the scale of AI infrastructure is large enough, custom computing will almost become an inevitable choice.

For hyperscale cloud vendors such as Google, Amazon, Meta, and Microsoft, they run huge and long-term stable AI workloads. Once a certain computing task reaches a large enough scale, there is an incentive to design dedicated hardware for it, remove unnecessary parts, and concentrate transistors, memory bandwidth and interconnection resources on the places that truly affect performance.

This is also why the ASIC capabilities accumulated by Broadcom for decades have suddenly become one of the most enviable assets in the entire semiconductor industry.

In the past, one of the biggest problems with ASICs was "high cost". From architecture definition, RTL design to physical implementation, verification, tape-out and mass production, an advanced ASIC often requires huge R&D investment. If only tens of thousands of chips are needed a year, redesigning a chip for a specific workload is hardly economically viable.

But when the investment scale of AI infrastructure rapidly grows from tens of billions of dollars to hundreds of billions of dollars, and the chip demand rises from tens of thousands to hundreds of thousands or millions, the entire economic model changes. If only tens of thousands of chips are needed a year, it is obviously not cost-effective to redesign an ASIC for a workload; but if hundreds of thousands, millions or even more chips are needed in the future, the one-time development cost can be diluted by the huge shipment volume.

This is also why almost all large cloud vendors today are strengthening their custom chip strategies.

In the future, the AI computing power market is more likely to be not an either-or choice between "GPU or ASIC", but gradually move towards division of labor: tasks that require versatility and rapid iteration will continue to rely on GPUs; mature workloads with sufficient scale will increasingly be handed over to custom ASICs. As the scale of the latter continues to expand, the competition around Custom Silicon has only just begun.

AMD: From game console chips all the way to AI ASIC

Before the latest rumors about Google TPU emerged, many people would not associate AMD with ASIC.

In fact, AMD has been engaged in Semi-Custom for more than ten years.

The Sony PlayStation 4 and Microsoft Xbox One launched in 2013 both adopted the Semi-Custom SoC co-developed by AMD for customers. The subsequent PlayStation 5 and Xbox Series X/S also continued to use AMD's custom chips. AMD's definition of the Semi-Custom business has always been very clear: combine its own CPU, GPU, multimedia and other IPs into customer-exclusive SoCs according to the specific needs of customers.

However, the Semi-Custom in the game console era is no longer comparable to the Custom Silicon required by today's AI data centers.

What has truly changed AMD's capability boundary are two important acquisitions around 2022.

In February 2022, AMD completed the acquisition of Xilinx, taking in FPGAs, Adaptive SoCs, AI Engines, as well as a large number of high-speed interface and programmable logic capabilities; in May of the same year, AMD completed the acquisition of Pensando Systems for about 1.9 billion US dollars, obtaining DPUs and software stacks related to networking, security and storage.

Looking further back, AMD happens to be one of the most active promoters of Chiplet and heterogeneous integration in the past decade.

So now when we look at AMD again, its technical building blocks are completely different: Zen CPU, Instinct GPU, Xilinx FPGA and Adaptive SoC, Pensando DPU and AI NIC, high-speed interconnection, as well as Chiplet and advanced packaging.

These capabilities used to serve server CPU, GPU, FPGA and network products respectively, but in the ASIC era, there is a new way to combine them: AMD does not necessarily have to sell a standardized EPYC or Instinct to customers, but can also recombine part of its IP into a customer-exclusive chip according to the customer's workload.

At AMD's 2025 Financial Analyst Day, Semi-Custom has been placed in a more important position, and Salil Raje, who is in charge of the Adaptive and Embedded Computing business, is also responsible for businesses including custom platforms.

Therefore, regarding this market rumor of Google TPU v10, AMD's capabilities are beyond doubt. What is really worth paying attention to is not just whether AMD has won a Google order. The key is whether AMD can replicate the Semi-Custom experience accumulated over the past decade and the technical capabilities supplemented by Xilinx, Pensando and Chiplet in recent years to the much larger data center AI ASIC market?

If the answer is yes, what AMD will sell to cloud computing giants in the future will not only be CPUs and GPUs. It can also sell Custom Silicon with "AMD inside". For AMD, this is a completely different market.

Intel and MediaTek have already entered the game

AMD is not the only one who has seen this market. In fact, Intel and MediaTek have already moved closer to AI ASIC, and compared with AMD, the business progress of the two currently has more clear revenue and project support.

Let's take a look at Intel first. In the second quarter of 2026, the revenue of "Other DCAI" in Intel's DCAI business reached 951 million US dollars, an increase of 304 million US dollars over the same period last year; the revenue in the first half of 2026 has reached 1.9 billion US dollars, a year-on-year increase of 533 million US dollars. Intel clearly explained in its 10-Q file that this part of the revenue growth is mainly driven by the increased demand for purpose-built silicon, that is, ASIC. This means that Intel's ASIC business is becoming a business with actual revenue scale.

Moreover, this is not the first time for Intel to develop ASICs for large cloud vendors. As early as 2021, Intel had jointly developed the ASIC version of IPU Mount Evans with Google; in April this year, the two sides announced further expansion of cooperation, and will continue to jointly develop custom IPUs based on ASIC, which are used to undertake network, storage and infrastructure processing tasks in data centers.

What makes Intel special is that it also has Xeon CPU, Ethernet, IPU, high-speed interface, EMIB/Foveros advanced packaging and Intel Foundry. In theory, it can further string together CPU, ASIC, packaging and even manufacturing.

A completely different path comes from MediaTek. In the past, the most familiar label for consumers about MediaTek was smartphone SoC. The Dimensity series almost defines the market's perception of the company.

But from a technical point of view, what the mobile SoC industry has cultivated over the past 20 years is exactly a capability very suitable for the Custom Silicon era: system-level integration of complex SoCs. A high-end mobile SoC itself is a highly complex heterogeneous system. CPU, GPU, NPU, ISP, memory controller, baseband, wireless communication and a large number of high-speed interfaces need to be integrated within a limited area and power consumption budget, while taking into account performance, cost, yield and mass production.

Now, this capability is being migrated to data centers. MediaTek has publicly demonstrated the data center ASIC technology portfolio including Arm Neoverse CPU, NPU, high-speed interconnection, SerDes, memory and advanced packaging, and clearly regards cloud AI ASIC as a new strategic market.

At the end of July this year, MediaTek further raised its 2026 AI data center chip revenue expectation to more than 2 billion US dollars, and predicted that the first custom AI chip will start mass production in the fourth quarter of this year; at the same time, it further increased its target share for the 2027 AI ASIC market to 15% - 20%.

According to previous reports from Reuters, MediaTek also participated in Google's next-generation AI chip project, but Google and MediaTek have not publicly confirmed the specific customer relationship.

So a very interesting situation has emerged. Broadcom and Marvell were originally the most typical players in the ASIC market; now AMD enters the market with CPUs, GPUs and Chiplets, Intel enters the market with CPUs, ASICs, packaging and even fabs, and MediaTek, Qualcomm and others migrate their years of accumulated complex SoC integration capabilities from mobile phones to data centers. Coupled with a series of domestic manufacturers such as VeriSilicon, ASR, Sinomicro and Corerain that are engaged in this business.

This once again shows that custom chips are no longer a niche chip design service business. It is gradually becoming another core industrial main line in the AI era.

The ASIC business has changed

If we compare the data center ASICs ten years ago with today's AI chips, one of the biggest changes is that the chips themselves are increasingly difficult to discuss independently from the system.

In the past, when designing an ASIC, the core problem was often the computing logic itself. Today it is completely different. Next to a large AI accelerator, HBM is required first. Scale-up interconnection is needed between chips, and Scale-out network is needed between cabinets; the front end also needs CPUs to undertake scheduling, data preprocessing and control tasks; further outside, there are NIC, Switch, Retimer and even optical interconnection. Packaging is no longer just the last process after chip manufacturing is completed, but more and more close to a part of the chip architecture itself.

Therefore, today's so-called "designing an AI ASIC" is actually often answering a series of questions at the same time: how to divide the computing die? Where does the CPU need to be placed? What capacity and bandwidth does HBM need? What interconnection is used between chips? How to design the Scale-up network? What bandwidth do NIC and Switch need? What advanced packaging is adopted? When will copper interconnection reach its limit? When must optics be used?

The evolution of Google's own TPU has already reflected this change. The 8th generation TPU released by Google this year has been split into TPU 8t for large-scale pre-training and TPU 8i for inference, reasoning and reinforcement learning, and both systems are equipped with Arm Axion CPU. TPU 8i also has 288GB HBM and 8601GB/s HBM bandwidth.

Google calls it part of the AI Hypercomputer. This term can well illustrate what is happening in today's AI chip industry. The object that really needs to be optimized is changing from Chip to System. Chip performance is still important, but what determines the efficiency of the entire AI cluster is the system efficiency formed by computing, memory, network, interconnection and software.

This is also the fundamental reason why AMD, Intel and MediaTek suddenly have the opportunity to enter the ASIC market.

Because when Custom Silicon evolves from "making a chip for the customer" to "recombining a whole set of computing systems according to the customer's workload", IPs that existed separately in the past such as CPU, GPU, DPU, SerDes, Chiplet and advanced packaging begin to have new value.

The more "technical building blocks" one has, the more likely one is to participate in the next-generation custom computing platform.

However, it is not as easy as it seems to grab Broadcom's business.

Broadcom's real moat: From electricity all the way to optics

What is really terrifying about Broadcom is that it has almost stepped on several of the most important data paths inside large AI clusters.

On one side is the Custom AI Accelerator. On the other side is a complete set of network and interconnection technologies: switching chips, NIC, PCIe, Retimer, SerDes, and further extended to optical devices, silicon photonics and CPO.

Broadcom's high-speed SerDes technology has been integrated into a large number of products such as Tomahawk switching chips, Thor NIC, PCIe Switch and Retimer.

By 2026, this territory will continue to expand outward. Broadcom has already mass-produced and shipped the 102.4Tbps Tomahawk 6, and at the same time has an Ethernet product portfolio for AI Scale-up, Scale-out and Scale-across; on the optical interconnection side, the company covers 200G/lane VCSEL, EML, continuous wave lasers, as well as CPO and NPO technologies. Tomahawk 6 has also derived the Davisson CPO solution, which combines the 102.4Tbps switching chip with co-packaged optics.

This is where Broadcom is really different. It not only participates in the design of XPU, but also masters a large number of core technologies that determine how the XPU exchanges data with the outside world. If the computing power of an AI chip doubles, but the data between chips cannot be transmitted in time, the system performance will not double; when a cluster expands from thousands of chips to hundreds of thousands or even millions of chips, the network may even be more important than the single chip itself.

In the past, data centers relied heavily on copper interconnection, but as the single-channel rate continues to increase, power consumption, signal integrity and transmission distance have begun to become limitations. AI clusters are gradually pushing optics closer to computing chips.

From pluggable optical modules, to Near-Packaged Optics, and then to Co-Packaged Optics, optics are constantly moving closer to the switching ASIC; in the future, if the Scale-up network continues to expand, optics may even move closer to the XPU itself.

Broadcom happens to stand at both ends of this technical migration path. On the "electrical" side, it has SerDes, Switch, NIC, PCIe and Custom XPU. On the "optical" side, it has VCSEL, EML, silicon photonics and CPO. This allows Broadcom to observe the technical bottlenecks at the three levels of computing chips, networks and optical interconnection at the same time, and carry out joint optimization at the system level.

This is also why Broadcom's ASIC moat is far more than just "chip design experience".

For customers like Google, what is really valuable is whether a supplier can complete architecture collaboration, physical design, SerDes, packaging, verification, mass production ramp-up and network support over several years, and finally deploy millions of chips stably into data centers. This capability cannot be replicated in two or three years by purchasing several IPs or forming an ASIC team.

In April this year, Broadcom and Google further signed a long-term agreement to continue developing and supplying Google's future generations of TPUs, and supply networks and other related components for Google's next-generation AI racks. The agreement term lasts up to 2031.

This incident itself also shows that the entry of companies such as AMD and MediaTek is currently more appropriately understood as the expansion of Google and even the entire Hyperscaler custom silicon ecosystem, rather than Broadcom being replaced.

At least for now, it is far from that step.

Final notes

The next stage of the AI chip industry may not simply belong to GPU, nor simply belong to ASIC. It is more likely to belong to companies that can cross the boundaries of chips, packaging, networks and systems. This is also why the business that Broadcom has been doing for decades has suddenly become a business that everyone wants to grab.

With the further refinement of the division of labor in the semiconductor industry chain, the competition among chip giants has evolved from the original individual combat of general hardware confrontation to all-round competition of ecological integration, core IP accumulation and custom delivery capabilities.