Intel, making a comeback in the storage industry? It could be far different from what you think.
"I just hired my good friend Suk-hee Lee, who used to run SK Hynix — so you can probably guess what I'm thinking about."
Recently, this remark by Intel CEO Pat Gelsinger on Celesta Capital's "TechSurge" podcast acted as a heavyweight signal, sparking industry speculation that the company is attempting to return to the memory market.
Pat Gelsinger opened up in a public interview: "In the past, I always believed that storage was a low-gross-margin commodity business and would never touch it; but the AI era is completely different. We are developing a brand-new memory architecture and exploring an integrated solution for 3D stacking of CPU and memory."
In fact, a personnel appointment at Intel in June this year also laid the groundwork for this: Suk-hee Lee, former CEO of SK Hynix, officially joined Intel as Executive Vice President of Intel Foundry Services (IFS), directly in charge of advanced packaging, system integration and backend manufacturing, reporting directly to CEO Pat Gelsinger.
What is even more thought-provoking is that this storage veteran was the core operator of SK Hynix's $9 billion acquisition of Intel's NAND flash business in 2020.
Combined with recent news and developments from Intel, the industry presents two polarized judgments.
The optimists believe that Intel, with its right to speak on the x86 CPU architecture, full set of advanced packaging technologies and IFS foundry platform, will break the monopoly of storage giants such as Samsung, SK Hynix and Micron on high-end storage once it achieves architectural-level integration of computing and memory, providing cloud vendors with a second supply chain option.
The cautious faction points out that Intel has no DRAM particle manufacturing capability at all, and its core media is completely dependent on external procurement. At best, it can only act as a packaging integration service provider and cannot shake the core discourse power of original storage manufacturers.
The Glory and Collapse of Intel's Storage Business
To understand today's strategic shift, we must first review the glory, collapse and legacy of Intel in the storage track over the past half century.
The company's storage history is almost half of the history of changes in the global semiconductor industry.
The starting point of Intel is storage.
In 1969, Intel launched the DRAM chip C1103, the world's first commercial DRAM chip, which became the world's best-selling semiconductor product by 1972. At its peak, it occupied nearly 90% of the global DRAM market share, making it a veritable storage overlord.
In that era, Intel was synonymous with storage — the glory of the DRAM business laid the technical and commercial foundation for this startup.
However, the glory did not last long.
In the 1980s, the Japanese semiconductor industry rose. Backed by the national system, Japanese semiconductor companies launched a price war with extreme cost control and production capacity scale, quickly seizing the global DRAM market. Intel's DRAM business continued to lose money, and its market share shrank rapidly.
By 1987, seven of the world's top ten DRAM suppliers were from Japan. Intel retreated steadily in this cost competition — the company's profit was still 198 million US dollars in 1984, but it fell to less than 2 million US dollars in 1985.
In 1985, then-CEO Andy Grove and Gordon Moore made a decision called "the most significant strategic shift in the history of semiconductors" by *The Economist* — to cut the memory business and go all in on the microprocessor business.
This retreat laid the foundation for Intel's dominance in the CPU field for the next 30 years, and also engraved its underlying perception of the storage business: standardized storage is a heavy-asset cycle trap, and Intel has no advantage in scale competition without technical barriers.
From then on, storage became Intel's "lost battlefield".
Advancing into NAND Flash, Divesting and Exiting with $9 Billion
More than 20 years after exiting the DRAM market, Intel, which was already famous in the CPU market, once again turned its attention to the storage track. This time, it chose NAND flash.
In 2005, Intel and Micron established a joint venture IM Flash to jointly develop and produce NAND flash, seizing the industrial trend of SSD replacing mechanical hard disks. At its peak, Intel's enterprise-level SSD market share ranked among the top in the world, and the 12-inch NAND wafer fab in Dalian was its core manufacturing base in Asia.
But the curse of the heavy-asset cycle came true again.
Samsung continued to expand production and launched a price war, the price of NAND flash plummeted periodically, the business was long-term meager profit or even loss, dragging down Intel's overall financial performance. At the same time, Intel's strategic focus shifted to advanced process, data center CPU and discrete GPU, and non-core assets needed to be divested to reduce burden.
In October 2020, Intel reached an agreement with SK Hynix to sell all its NAND flash business for a total price of 9 billion US dollars, including the SSD product line, Dalian wafer fab and related intellectual property rights. The transaction was delivered in two phases:
The first phase of delivery was completed in December 2021, SK Hynix paid 7 billion US dollars and took over the SSD business and Dalian fab assets;
The second phase of delivery was completed in March 2025, SK Hynix paid the remaining 2 billion US dollars to obtain NAND wafer design IP and R&D team, the transaction was completely closed, and the corresponding business operated independently under the Solidigm brand.
At this point, Intel completely withdrew from the general NAND market and made a second strategic retreat from the main storage battlefield. The operator of this transaction was exactly Suk-hee Lee, then CEO of SK Hynix.
Putting All Eggs in the Optane Basket, Still Failing to Survive
While selling NAND, Intel retained the Optane business, which can be regarded as its third storage exploration and the most technically ambitious attempt.
Optane is based on 3D XPoint media, positioned as storage-class memory (SCM) between DRAM and NAND, claiming that its read and write speed is 1000 times that of NAND and its service life is far longer than that of flash memory. It aims to fill the gap in the storage hierarchy and reconstruct the data center storage architecture, and is regarded as the biggest breakthrough in storage chips in 25 years.
From a technical point of view, Optane is undoubtedly a success. It shows overwhelming performance in scenarios such as databases, high-frequency trading, and real-time computing, and the persistent memory mode pioneered the realization of memory-level capacity expansion.
But in terms of commercialization, Optane still suffered a complete failure. Due to excessive cost, difficult ecological adaptation, and failed promotion in the consumer market, it was ultimately highly praised but not well received. In 2021, Micron terminated 3D XPoint R&D and sold the fab, and in 2022, Intel officially shut down the Optane business.
Several attempts have failed one after another. Intel's resume in the storage field can be described as full of regrets.
Reviewing Intel's ups and downs in storage over the past decades, the underlying logic of its failures is basically the same:
Mode Mismatch: Directly stepping into the production of standardized general-purpose particles, falling into the quagmire of heavy assets, strong cycles, and price wars, which is contrary to Intel's gene of asset-light IP R&D;
Position Deviation: The technical route is ahead of the industrial ecology, and it cannot form a large-scale commercial closed loop;
Collaboration Fragmentation: The storage business and processor business fought their own battles, and there was no value linkage between computing and storage at the system architecture level.
However, these trial and error in the storage field are not completely useless. It has accumulated and retained a large number of relevant technologies and experiences for Intel. In particular, the valuable experience of Optane technology in memory hierarchy architecture design, persistent memory software and hardware collaboration, and storage and computing collaborative optimization, these technical precipitations may be the underlying heritage that supports Intel's brave exploration again today.
Why Turn Around Again?
For the news mentioned at the beginning, Intel's choice to return to storage at this moment is by no means a whim, but an inevitable result of the qualitative change of the underlying industrial logic under the AI wave.
In 2026, storage chips are in an unprecedented super boom cycle. Omdia predicts that the global semiconductor market will grow by 94.1% year-on-year in 2026, and storage chip revenue will account for more than 50% of the total global semiconductor revenue. JPMorgan Chase predicts that the global storage market will be about 969 billion US dollars in 2026 and will reach 1.82 trillion US dollars in 2028. Goldman Sachs predicts that HBM demand for custom ASIC AI chips will soar by 82%.
In terms of the HBM market, according to data from SEMI and TrendForce, the global HBM market size is expected to reach 54.6 billion US dollars in 2026, a year-on-year increase of 58%, accounting for nearly 40% of the overall DRAM market size; it will exceed 102 billion US dollars in 2028, with a three-year compound growth rate as high as 44%.
Imbalance between supply and demand is the core feature of this round of cycle. Although the three major original manufacturers of Samsung, SK Hynix and Micron have tilted 70% of new DRAM production capacity to HBM, the overall supply and demand gap is still as high as 50%-60%, and the full-year HBM production capacity in 2026 has been fully pre-purchased by NVIDIA, AMD and leading cloud vendors.
More critically, there is a qualitative change in the value logic. Pat Gelsinger admitted on the podcast: "I used to always say don't invest in storage because it's a commodity business, but now everything has changed." He characterized AI's pull on storage as a "strategic" opportunity.
Over the past 50 years, the essence of storage chips has been "commodities" — following JEDEC general standards, standardized production, large-scale sales, driven by price cycles, which is a typical strong-cycle heavy-asset business. Now, with the explosive increase in demand for storage bandwidth in AI systems, storage has changed from a "supporting role" to the performance bottleneck and value highland of AI infrastructure.
On the one hand, the value focus of storage in the AI era has shifted from capacity to bandwidth and energy efficiency. New types of storage such as HBM are no longer standardized consumables, but system-level components deeply bound to computing power chips; on the other hand, in the post-Moore era, the marginal benefit of improving performance solely through process technology is decreasing, 3D stacking and heterogeneous integration have become the main source of performance gains, and the physical boundary between computing and storage is dissolving.
As Pat Gelsinger said, adding memory directly on top of the CPU "makes perfect sense", and there are many ways the two can be stacked together.
Facing the inherent shortcomings of the von Neumann architecture and the challenges of memory, the mainstream solution in the current industry is to shorten the data transmission distance and increase bandwidth through HBM stacking, Chiplet heterogeneous integration, and CXL memory expansion. But these are only transitional solutions. The real ultimate direction is to break the boundary between computing and storage at the physical level and achieve architectural-level integration.
This brings a new window of opportunity for Intel. At the same time, this also means that Intel's return to storage this time may not follow the old path of building its own wafer fabs to produce general-purpose storage particles. Its battlefield has shifted from particle manufacturing to architecture definition and system integration.
Because the industry does not lack manufacturers that can manufacture DRAM particles, but there is a lack of players who have top-level processor architecture definition capabilities, self-developed advanced packaging technologies, and wafer foundry mass production capabilities to do system-level integration of computing and storage.
After divesting flash memory and terminating Optane, Intel once missed the core track of the AI wave. Now, the storage industry is in a critical period of innovation, which is often the window period for pattern reshaping.
Pat Gelsinger emphasizes long-termism and pays attention to the construction of industrial platforms in the next 10-15 years. This time, Intel doesn't want to miss it again.
What Paths Does Intel Have to Return to Storage?
After clarifying the background of the times, analyzing Intel's specific paths may become relatively clear.
Inviting the Person Who "Bought Its Own Business"
As mentioned above, Intel announced in June this year the appointment of former SK Hynix CEO Suk-hee Lee as Executive Vice President of the Foundry Business, with overall responsibility for advanced packaging, system integration, backend technology development and backend manufacturing, reporting directly to Pat Gelsinger.
This personnel appointment is full of drama — the representative of SK Hynix who led the acquisition of Intel's NAND business in 2020 was Suk-hee Lee himself. Now, the person who bought Intel's last memory business has been invited back to run Intel's department closest to memory.
More notably, Suk-hee Lee is not an outsider who was parachuted in. He worked as a process integration engineer at Intel from 2000 to 2010, participated in the development of nodes from 130nm to 32nm, and won the Intel Achievement Award three times. After that, he led SK Hynix and led the development of HBM. During his tenure as CEO of SK Hynix from December 2018, the company's HBM market share rose to about 60%, and its market value grew from about 37 billion US dollars to more than 80 billion US dollars.
This is the sentence at the beginning of the article, Pat Gelsinger specifically pointed out this appointment as a signal on the podcast: "I just hired my good friend Suk-hee Lee, who used to run SK Hynix — so you can probably guess what I'm thinking about."
Taking IFS Foundry as the Carrier, Focusing on HBM Packaging
The author believes that the easiest path to implement and generate revenue the fastest is for Intel to rely on IFS advanced packaging capabilities to carry out deep HBM collaboration with SK Hynix.
Suk-hee Lee's joining can be regarded as a trust bond for Intel and SK Hynix to deepen cooperation. In the current situation of insufficient TSMC CoWoS production capacity, the cooperation model between the two sides is very clear: SK Hynix provides HBM storage particles, Intel provides EMIB 2.5D packaging and Foveros 3D packaging technologies, heterogeneously integrates HBM with Xeon CPU, Intel GPU and even third-party AI chips, and delivers integrated packaged finished products to customers.
For Intel, this model has multiple values:
First, it increases the added value of the IFS foundry business, upgrading from pure logic wafer foundry to a total solution of "logic chip + storage particle + advanced packaging", raising the gross profit margin of the foundry business;
Second, it ensures the stable HBM supply of its own CPU and GPU product lines, gaining supply chain advantages during the industry shortage cycle;
Third, it accumulates mass production experience in collaborative packaging of storage and logic chips, paving the way for the next generation of stacked memory architecture.
ZAM Stacked Memory, Building an Alternative Architecture for HBM
In February 2026, Intel announced cooperation with SAIMEMORY, a subsidiary of SoftBank, to develop ZAM (Z-Angle Memory) technology.
The core idea of ZAM is to stack DRAM chips at an oblique angle above the processor, shorten the data transmission path through Z-Angle interconnection technology, and break through the memory wall at the physical level. According to the publicly available technical parameters, ZAM can reduce power consumption by 40%-50%; the mass production cost is only 60% of HBM; the maximum capacity of a single chip can reach 512GB, which is 2 to 3 times that of existing HBM, and its heat dissipation performance is better than traditional vertical stacking solutions.
According to the pre-release abstract leaked from the official VLSI conference list, ZAM's "Via-in-One TSV" (integrated through-silicon via) architecture can achieve an ultra-high memory bandwidth of about 0.25Tb/s/mm², and the data transmission power consumption is controlled below 0.35W/mm².
The project was officially launched in the first quarter of 2026, plans to launch prototype products in 2027, and achieve full commercial mass production around 2030. It has now received government funding support from Japan's NEDO, and Powerchip has also joined the camp to participate in process R&D. In terms of cooperation division of labor, SAIMEMORY is responsible for technical design and intellectual property management, Intel outputs 3D stacking and memory architecture experience, and Powerchip and Japan's Shinko Electric provide trial production and manufacturing support.
It is worth noting that ZAM does not intend to replace all H