Has the "next gold mine" in the storage sector suddenly lost its appeal?

Over the past two years, the spotlight in the storage industry has been fixed on HBM — the massive demand spurred by AI large model training has turned high-bandwidth memory into the hottest track in the semiconductor sector, with prices soaring and production capacity unable to meet market demand. However, entering 2026, another technological concept is moving from the industry's periphery to center stage: CXL.

So what exactly is CXL, and how will it carve out a new niche in the memory market dominated by industry giants?

01 

CXL, Stepping into the Spotlight 

The large-scale breakout of any technology first requires a sufficiently compelling trigger. The catalyst for CXL is a price list that has left data centers unable to remain complacent.

Consider a set of statistics:

Since the second half of last year, global memory chip prices have continued to climb. Data from East Money Choice shows that in the international market, the average contract price for 16Gb DRAM chips used in DDR5 rose from $4.8 per unit in May 2025 to $37.5 per unit in May 2026, representing a 681% increase over the year. During the same period, the average selling price of mainstream DDR5 16GB consumer memory modules skyrocketed from around 800 yuan in mid-2025 to over 4,000 yuan currently, a more than 400% increase within six months.

In the server sector, the price of 256GB DDR5 memory modules has exceeded 50,000 yuan. Data indicates that the unit price of 64GB DIMM modules has risen by a cumulative 350% from Q3 2025 to Q1 2026, and the total increase is expected to expand to 500% by Q3 2026.

What we need to focus on here is not "the price increase itself," but the structural nature of this price surge. The underlying driver of this round of memory price hikes since 2025 is the siphon effect of AI servers on DDR5 — large model inference requires massive amounts of memory to accommodate enormous model parameters and KV Cache, while server CPUs have a limited number of memory channels, so demand can only be met by deploying high-capacity memory modules. When the demand side sees a collective upgrade of millions of servers, while the three major original manufacturers have allocated the majority of their production capacity to HBM, the supply-demand gap for DDR5 is no longer cyclical, but structural.

It is in this gap that CXL has transformed from a "next-generation technology" into a "current solution."

Before delving into CXL, let's first understand a key definition. NUMA (Non-Uniform Memory Access) is a memory architecture design suitable for multi-processor systems. In a NUMA system, each CPU (more accurately, each NUMA node) has its own "local" memory, and accessing this memory incurs low latency. Accessing "remote" memory on other nodes requires traversing the NUMA bus, resulting in poor latency and bandwidth. This design splits memory — the most valuable resource — into isolated islands, both physically and logically.

CXL (Compute Express Link) technology is a new type of high-speed interconnection technology designed to deliver higher data throughput and lower latency to meet the demands of modern computing and storage systems. It was initially jointly launched by Intel and AMD and received extensive support from companies including Google and Microsoft. This means enterprises no longer need to pay a premium to equip every CPU with full-capacity local DDR5 memory. Instead, they can deploy standardized memory resource pools centrally via the CXL bus, enabling computing nodes to elastically allocate memory on demand.

As such, the primary application scenarios for CXL lie in artificial intelligence, high-performance computing, and data centers.

Since its release in 2019, the CXL protocol has undergone multiple iterations, and it is closely tied to PCIe versions.

CXL 1.0 was released in March 2019, built on PCIe 5.0 technology. CXL 2.0 was released in November 2020, also based on PCIe 5.0, and introduced memory pooling, switching capabilities, persistent memory, and security features. CXL 3.0 was released in August 2022, based on PCIe 6.0, with per-channel bandwidth increased to 64 GT/s, and introduced the Fabric concept, supporting multi-level switching, true memory sharing, and peer-to-peer device communication. CXL 3.1 was released in November 2023, making incremental updates on the basis of CXL 3.0 to enhance fabric scalability and trusted execution environment (TEE) support. CXL 3.2 was announced in December 2024, optimizing the monitoring and management of CXL storage devices and extending security capabilities via the Trusted Security Protocol (TSP). The CXL 4.0 specification was released in November 2025, achieving a data rate of 128 GT/s.

It is no exaggeration to say that CXL has brought about a revolution to data centers.

First, as defined by the CXL Consortium, the standard uniformly supports three categories of devices: 1. High-speed cache devices, such as smart network cards; 2. General-purpose computing and acceleration chips, including CPUs, GPUs, DPUs, SoCs, and various AI/FPGA accelerators; 3. Memory expansion controllers, covering DRAM, new persistent memory, and NAND flash, typically used as memory buffers to expand bandwidth or capacity. At this stage and over the next 2-3 years, the most core and practical value of CXL lies in expanding server memory resources at a more economical cost and improving data transmission efficiency. Its deeper significance can be glimpsed from CXL's evolution roadmap.

Second, as mentioned earlier, CXL 2.0 and subsequent versions have introduced memory pooling and sharing capabilities, which means CXL 2.0 allows the memory resources of multiple servers to be aggregated into a pool through a switch and dynamically allocated to different computing nodes on demand. This is a key step for the technology to expand from a single machine to clusters. However, to achieve global pooling at the rack level or even data center level, the large-scale commercial deployment of CXL 3.0 and later hardware (supporting Fabric multi-level switching) is required.

Third, the industry is currently exploring NVDIMM (Non-Volatile Dual In-line Memory Module) and solutions based on new storage media (such as MRAM and ReRAM). In the future, it is expected that these can be used as remote persistent memory in conjunction with the CXL interface.

Fourth, as CXL is gradually implemented, a more imaginative evolution direction is its deep integration with data processing units (IPU/DPU). Currently, when CPUs and DPUs collaboratively process storage and network tasks, data needs to be copied multiple times between the memory of the two, consuming CPU cycles and increasing latency. CXL supports the establishment of a unified, cache-coherent shared memory domain between CPUs and DPUs. This means DPUs can directly read pending data from CPU memory and write back processed results directly, eliminating explicit data movement. This capability will improve the efficiency of tasks such as storage offloading, compression/decompression, and encryption/decryption by an order of magnitude.

In short, CXL is not just an interface standard — it represents a philosophical shift that transforms memory from the "private property" of CPUs into a data-center-level "public resource."

02 

Meta, Exposing the Pain Point 

In CXL memory systems, the Memory eXpander Controller (MXC) is the absolute core component. It is a high-performance dedicated integrated circuit (ASIC) or system-on-chip (SoC) located on CXL memory modules (such as E3.S or PCIe AIC form factors). Recently, at the ISCA 2026 International Symposium on Computer Architecture, Meta publicly unveiled its self-developed Vistara custom chip solution. This is a CXL ASIC specifically designed to reuse DDR4 memory from decommissioned servers, by connecting DDR4 memory modules from old servers to new-generation DDR5 servers to build a shared memory pool, which can be deployed in hyperscale infrastructure covering millions of servers. The paper published by Meta shows that this solution can reduce the number of servers required for some AI inference workloads by up to 25%, and cut the average latency of distributed caches by 29%.

Meta's paper reveals a widespread resource mismatch problem in data centers: the expected service life of servers is typically 3 to 5 years, but the physical lifespan of server-grade DRAM chips can reach 7 to 10 years. This means a large amount of DDR4 memory with still good performance will be idled or even scrapped as the entire server units are decommissioned.

More critically, in Meta's own infrastructure, about 40% of its servers — numbering in the millions — cannot continue to host new AI workloads due to memory capacity limitations. Meanwhile, massive amounts of DDR4 memory are left unused. Against the backdrop of skyrocketing DDR5 memory prices and tight supply, this dilemma of "old memory lying idle while new memory is unaffordable" represents a huge waste of resources for hyperscale internet companies with annual capital expenditures of tens of billions of dollars.

In addition, cloud vendors such as Google have also begun deploying CXL in their data centers, and are installing controllers to manage data traffic between CPUs and large external memory pools. NVIDIA plans to support the CXL 3.1 standard in its Vera CPU, which will be launched later this year. This move is regarded by the industry as the largest practical test of CXL to date.

Therefore, the "reuse" of CXL is perfectly timed.

03 

CXL, The Era Has Arrived 

Currently, there are only a handful of vendors capable of providing mature commercial products, which are mainly divided into two categories: one is independent interconnection chip design companies, and the other is original storage manufacturers attempting vertical integration.

In terms of interconnection chip design companies, Montage Technology, leveraging its deep expertise in DDR4/5 buffer chips, has expanded into the CXL memory controller field and established a first-mover advantage. It released its first CXL MXC chip supporting the CXL 2.0 standard in May 2022. In 2024, it completed the R&D of the mass-produced version of its first-generation CXL MXC chip. In January 2025, the chip successfully passed CXL 2.0 compliance testing and was included in the first batch of CXL 2.0 compliant supplier lists announced by the CXL Consortium. The memory vendors Samsung Electronics and SK Hynix, who were selected in the same batch, both used Montage Technology's MXC chips in their tested products. In September 2025, the company released the new-generation MXC chip M88MX6852 designed based on the CXL 3.1 standard, and began sending samples to key customers for testing. In addition, leading interface IP enterprises Microchip, Marvell, and Rambus are also major competitors in this field.

Back in August 2022, Microchip announced the expansion of its serial-attached storage controller product line, launching the new SMC 2000 series intelligent storage controllers based on CXL. Marvell's CXL strategy is more like a series of acquisitions. In 2022, Marvell announced the acquisition of Tanzanite in an all-cash transaction to enhance its cloud-optimized CXL product portfolio. In January this year, Marvell announced that it had reached a definitive agreement to acquire XConn Technologies, a supplier of advanced PCIe and CXL switching chips, for approximately $540 million. Rambus has also launched its own CXL 3.1 controller chip, but its larger business remains in IP licensing.

On the part of original storage manufacturers, they mainly deploy CXL by purchasing CXL controllers and integrating them into memory modules before delivering to customers. Previous reports indicated that Samsung named its CXL DRAM module CMM-D, and planned to start mass production of memory products compliant with the CXL 3.1 standard as early as the fourth quarter of 2026. SK Hynix completed customer certification of CXL 2.0 standard products in 2025, and exhibited the CMM-DDR5 CXL memory module for AI servers. Micron launched the CZ120 memory expansion module based on the CXL 2.0 standard as early as 2023.

However, a critical turning point occurred in July 2026. According to South Korean media reports, Samsung Electronics, SK Hynix, and Micron Technology have all scaled back or abandoned their self-developed CXL controller commercialization plans. Among them, Micron has closed its self-development department and adopted PrimeMass's solution; SK Hynix has terminated its self-development project, with the team shifting focus to the PIM (Processing-in-Memory) field; Samsung has removed self-developed controllers from its commercialization roadmap, retaining only cutting-edge R&D work.

The fundamental reason for this collective shift by the three major manufacturers may be the concern that their self-developed high-end CXL controllers will "cannibalize" their core profit source — general-purpose DRAM modules. At the same time, data center customers prefer to adopt a "discrete" architecture, which means purchasing third-party controllers and general-purpose DRAM separately for combination to reduce costs.

It is worth noting that the original storage manufacturers have not abandoned CXL technology itself, but only abandoned the commercialization plans for self-developed controllers, instead turning to purchase products from professional chip design companies. This strategic shift has in turn strengthened the market position of independent chip design companies such as Montage Technology.

Industry analysis suggests that 2026 marks the starting point for large-scale CXL deployment, and 2027 is expected to become the first year of large-scale commercial use of CXL. With the mass production of server CPU platforms supporting CXL 3.0, more advanced memory pooling solutions will be gradually implemented, and the penetration rate of CXL in data centers is expected to rise rapidly in the coming years.

This article is from the WeChat public account "Semiconductor Industry Review" (ID: ICViews), author: Feng Ning, published with authorization from 36Kr.