Glass packaging is really coming.

Several years ago, glass core substrates were already regarded as a potential solution for high-end packaging. But why, after so many years of discussions, has glass packaging still not achieved real large-scale application?

The reason is that "glass packaging" has never been a single technology that can be independently conquered and fully replaced. Glass can be used not only as a temporary carrier, but also as a permanent core layer, interposer, passive device platform, and even optical interconnection structure of the packaging substrate. Different applications correspond to different material systems, manufacturing processes, and industrial chain divisions, and respectively face challenges such as through-glass vias, metallization, warpage control, yield, and mass production costs. Therefore, glass does not suddenly enter the packaging field at a certain point in time, but gradually penetrates into the chip packaging system through different roles and along different technical paths.

Today, this process is accelerating significantly. From Intel, TSMC, Samsung, SK, LG, to UMC, ASE Group, Corning, AGC, and Innolux, more and more industrial chain players from the chip manufacturing, packaging and testing, materials, and display panel industries are including glass in their advanced packaging roadmaps. The previously scattered material exploration, process development, and application verification are gradually forming a clearer industrial chain.

What glass truly brings is probably more than just a material replacement, but a profound reshaping of the boundaries of the advanced packaging industry and the supply chain landscape.

Physical Bottles Push the Industry into the "Glass Era"

Over the past decades, the semiconductor industry has measured technological progress primarily by whether transistors can continue to shrink. But in the era of AI chips, more and more performance improvements are not achieved within a single chip, but from the collaboration of GPUs, CPUs, HBM, network chips, I/O Dies, and various Chiplets in the same package. Advanced packaging has evolved from a "back-end process" after chip manufacturing to a key link that directly determines computing power density, memory bandwidth, power consumption, and system cost.

The reason why glass has attracted attention is not first and foremost because it is a new material, but because the packaging size of AI chips is rapidly approaching the limits of traditional materials and manufacturing systems.

TSMC has been expanding its CoWoS from the early size of approximately one reticle. In 2026, TSMC began producing CoWoS with a size of 5.5 reticles, and plans to launch a 14-reticle size version in 2028, which can theoretically integrate about ten large-scale computing chips and 20 sets of HBM. The company will continue to push for larger sizes in 2029.

When the packaging area is only tens of millimeters square, the shrinkage, expansion, and warpage of organic carriers can still be compensated through material formulations, layered structures, and process parameters. However, as the packaging gradually expands to 100 millimeters or even larger scales, problems will increase non-linearly: the inconsistent coefficients of thermal expansion between different materials will cause the carrier to deform during temperature cycles; the larger the packaging area, the easier it is for alignment errors between multilayer circuits to accumulate; the stress between copper circuits, resin dielectrics, and the core layer will also affect the yield of micro-bumps, RDL, and chip mounting.

Intel summarizes the main limitations of traditional organic materials as shrinkage, warpage, power delivery, and interconnection density. Its announced technical goal for glass substrates is to raise the packaging design rules by an order of magnitude, supporting higher-density interconnections and larger-scale Chiplet combinations. Intel believes that the higher stiffness, flatness, and dimensional stability of glass can enable packaging to continue evolving toward larger areas, finer circuits, and higher I/O density.

A common misconception needs to be clarified here: the advantages of glass do not mean that it "conducts heat better than silicon or metals". The thermal performance emphasized by manufacturers such as Samsung Electro-Mechanics and AGC mainly refers to the fact that glass has a low or adjustable coefficient of thermal expansion, and its dimensions are more stable during temperature changes, thereby reducing carrier warpage and interlayer misalignment. It solves the thermo-mechanical stability problem, rather than directly replacing heat sinks, cold plates, or thermal interface materials.

In addition, glass itself is an insulating material with good high-frequency characteristics and low dielectric loss. In high-speed SerDes, switch chips, HBM, and future co-packaged optics, as signals pass through more and more circuits with increasingly higher frequencies, the dielectric properties of packaging materials will directly affect insertion loss, crosstalk, and power consumption.

Therefore, the core value of glass is not a single parameter, but its ability to simultaneously meet four new requirements for advanced packaging: larger area, more stable dimensions, higher-density interconnections, and better high-frequency electrical performance.

Glass Enters Chip Packaging

In at Least Five Different Forms

However, glass packaging is not a unified technical route. On the contrary, it includes at least five different industrial forms: Temporary Glass Carrier, Glass Core Substrate, Glass Interposer, TGV, and GlassBridge. Only by distinguishing these concepts first can we see what manufacturers are really competing for.

The first form is the temporary glass carrier

In wafer-level and panel-level fan-out packaging, chips, molding compounds, and RDL structures are usually thin and prone to warpage or damage during thinning, exposure, electroplating, and bonding processes. Therefore, they need to be laminated onto a flat and stable glass first. After the process is completed, this glass will be removed through laser or other debonding methods and will not remain inside the final chip. This kind of glass is essentially a process tool. In other words, the fact that a panel-level packaging production line "uses glass" does not necessarily mean that the final delivered chip contains glass. Its key indicators include flatness, total thickness variation, surface roughness, coefficient of thermal expansion, and compatibility with temporary bonding and debonding materials.

AGC has been mass-producing and supplying glass carriers for wafer-level and panel-level packaging, with products covering 300mm wafers and approximately 500mm square panels. Corning has also long provided precision glass carriers for fan-out packaging, thin wafer processing, and large-sized panels.

The second form is the glass core carrier that permanently remains inside the package

Traditional FC-BGA packaging substrates usually consist of a thick organic core layer, as well as multiple layers of build-up dielectrics and copper circuits on both sides. The glass core carrier does not turn the entire packaging substrate into a single piece of glass, but replaces the middle organic core layer with glass, and then fabricates ABF or other dielectric layers, copper interconnections, and pads on its top and bottom.

Intel, Samsung Electro-Mechanics, Absolics under SKC, and LG Innotek are currently competing mainly in this direction.

The glass core layer has higher stiffness and more stable dimensions, so it can support larger FC-BGA packages and finer build-up circuits. However, at the same time, there are still differences in the coefficient of thermal expansion between glass, resin, copper, and chips, and interlayer peeling and thermal stress will not disappear automatically just by switching to glass. The glass core will not make ABF, low-dielectric resin, and PCB disappear, but change the material system of the middle core layer of the packaging substrate. AGC stated in its business description that even if the glass core becomes popular, PCB and related resin materials will still exist, and the two are not a simple complete substitution relationship.

The third form is the glass interposer

The interposer is located between the computing chip, HBM, and packaging substrate, and is mainly responsible for high-density lateral interconnection. Currently, high-end AI chips extensively use silicon interposers because the silicon manufacturing process is mature and can fabricate high-density TSVs and fine RDLs.

The glass interposer replaces TSV with TGV, and fabricates RDLs on both sides of the glass to connect the GPU, HBM, and Chiplets. Compared with silicon interposers, glass can be processed in larger sizes and has good high-frequency insulation properties; but its circuit density, TGV metallization, mechanical reliability, and manufacturing ecosystem are not yet as mature as silicon processes.

LG Innotek publicly stated that the company is simultaneously developing glass substrates and glass interposers, with technical focuses including high-aspect-ratio TGV, plating adhesion, thickness planarization, and fine circuits, aiming to push for mass production between 2027 and 2028.

The fourth form is the glass passive device and functional integration platform

Glass is more than just a mechanical support material. Through TGV, thin film deposition, and RDL processes, inductors, capacitors, filters, antennas, sensors, MEMS, and integrated passive devices can also be fabricated on glass.

Due to its good insulating properties and low parasitic loss, this technology has a long development history in RF front-end, millimeter wave, MEMS, and sensor packaging. AGC's current TGV products are targeted at glass interposers, 3D glass IPD, MEMS, and sensors.

AI packaging has increasingly higher requirements for power integrity. In the future, decoupling capacitors, inductors, optical waveguides, and other functional structures may also be integrated on the glass core or glass interposer. At that time, the value of glass will no longer be limited to replacing organic materials, but to moving more system functions into the package.

The fifth form is the optical GlassBridge for silicon photonics and CPO

Corning's GlassBridge is easily misunderstood. Judging from its name, it seems similar to the local interconnection bridges in Intel's EMIB or ASE's FOCoS-Bridge. However, Corning pointed out in its "GlassBridge Technical Statement" released in July 2026: "GlassBridge is a technical concept that aims to explore how to apply Corning's proprietary ion exchange (IOX) optical waveguide capabilities in flat glass to solve the fiber-to-chip coupling challenges in the fields of photonics and semiconductor packaging." In other words, GlassBridge is mainly used to connect optical fibers and silicon photonic PICs, rather than the copper interconnection structure that connects GPUs and HBMs.

They further pointed out that this technology is still in the early stage of development, has not yet been commercialized, and has not reached commercial-scale production. On the premise of future commercialization, GlassBridge can serve as one of the alternatives to the traditional Fiber Array Unit (FAU) in specific application scenarios, based on density requirements, assembly processes, and other specific application factors. It is not positioned as a universal solution to replace Fiber Array Units (FAU) in all application scenarios, nor is it intended to replace optical fibers. Optical fibers will remain the foundation of artificial intelligence and data center infrastructure.

Therefore, although Intel's EMIB, ASE's FOCoS-Bridge, and Corning's GlassBridge all contain the word "Bridge" in their names, the former two mainly solve electrical interconnection problems, while the latter solves optical coupling, and they cannot be confused.

Heroes Compete for the Throne

Manufacturers Are Betting on Different Positions in the Industry

Whether it is foundry giants, South Korean semiconductor chaebols, OSAT (packaging and testing plants), or material and display panel manufacturers, a full-scale battle for supply chain positioning around "glass" has already broken out.

Now, if we look at the positions of major manufacturers, the picture becomes relatively clearer.

(1) The Foundry Camp

Intel: The Aggressive Route Pioneer

Intel is one of the earliest chip manufacturers to elevate the glass core carrier to a system-level technical route. This is related to Intel's long-term promotion of EMIB, Foveros, and multi-chiplet packaging. Intel's goal is not to independently manufacture a single piece of glass, but to make glass a basic platform that carries EMIB local silicon bridges, vertical stacking, embedded passive devices, power delivery structures, and future optical I/Os.

Intel's published internal test results show that compared with traditional organic substrates, glass can reduce pattern distortion by about 50% and support up to ten times the interconnection density, while facilitating the fabrication of larger packages and the integration of inductors, capacitors, and optical interconnections. Intel's announced glass substrate plan is targeted at "the second half of this decade", claiming that it can achieve an order-of-magnitude improvement in design rules, supporting larger Chiplet systems and higher interconnection density. The characteristic of this route is architecture-first: Intel starts by determining how many Chiplets, I/Os, and transistors future processors need to integrate, and then reversely deduces the carrier material and packaging process. Its glass technology will be combined with EMIB, Foveros, and CPO, rather than existing in isolation.

TSMC: Steady Defense and Undercover Layout

TSMC's current attitude is more cautious than Intel's. TSMC is not in a hurry to replace CoWoS, but is adding a low-cost expansion route.

At the earnings conference in the first quarter of 2026, C.C. Wei stated that TSMC is building a CoPoS pilot line and expects it to enter production in several years, but the main force of advanced packaging is still large-size CoWoS. At the earnings conference in the second quarter of 2026, analysts further inquired about the progress of glass cores, glass substrates, and glass carriers. C.C. Wei's response was that most of the current products still use CoWoS, TSMC is developing an alternative solution to reduce costs, and is cooperating with carrier suppliers. It is expected to take about another year to mature before it can be jointly introduced into production with customers.

At the same time, TSMC is continuously expanding CoWoS. It has produced the 5.5-reticle size version in 2026 and plans to expand it to 14 reticles in 2028, which can accommodate about ten large computing chips and 20 sets of HBM.

DIGITIMES, citing supply chain and technical data, reported that TSMC is cooperating with Ibiden, Innolux, and others to verify the next-generation glass core carrier for CoWoS, including warpage, CTE, impedance, and reliability of large-size carriers. TSMC did not confirm in its response whether it will specifically adopt a glass core, glass interposer, or only use a glass carrier, nor did it publicly confirm its suppliers.

Samsung: The Group-style Panel-level Breakout

Samsung is leveraging its in-house foundry, display panel, packaging substrate, and material supply chain to simultaneously advance both the glass interposer and glass core carrier routes.

Among them, The Elec reported on July 11, 2026, that Samsung Electronics and Samsung Display are jointly developing glass interposers, which is expected to produce prototypes as early as 2026 and carry out business promotion for global hyperscale technology companies. The purpose is not only to reduce the cost of silicon interposers, but also to establish a "Fabric" ecosystem that integrates foundry and advanced packaging to compete with TSMC's CoWoS and CoPoS.

Samsung Display has also established a dedicated R&D team for glass interposers, with the focus expected to be on utilizing the existing metal deposition, lithography, exposure, and etching capabilities of panel factories to fabricate redistribution layers on glass.

Samsung Electro-Mechanics is advancing another product — the glass core packaging substrate. It replaces the original organic core layer in the FC-BGA packaging substrate with glass, and still fabricates build-up dielectric layers and copper circuits on the top and bottom of the glass. This piece of glass is located inside the packaging substrate, rather than acting as an interposer between the chip and the packaging substrate to undertake ultra-high-density interconnections.

Samsung Electro-Mechanics has built a pilot line for glass packaging substrates at its Sejong site, and began to promote customer sample deliveries in 2025, with the original target of mass production after 2027. In November 2025, Samsung Electro-Mechanics also signed a memorandum of understanding with Sumitomo Chemical and Dongwoo Fine-Chem, planning to establish a glass core joint venture. Samsung Electro-Mechanics will hold a majority stake, with the initial production base planned to be located at Dongwoo Fine-Chem's Pyeongtaek plant; Samsung Electro-Mechanics' Sejong pilot line will continue to undertake sample production and process verification.

It can be said that Samsung has formed a clear internal division of labor: Samsung Electronics is responsible for architecture, foundry integration, and customers; Samsung Display is responsible for RDL processes on large-size glass; Samsung Electro-Mechanics is responsible for glass core packaging substrates; and external material and equipment manufacturers are responsible for TGV, copper via filling, and glass processing.

UMC: The "Surprise Soldier" That Avoids Front-end Processes and Focuses on the Mid-to-back End

UMC is a very noteworthy player in this round of glass packaging layout.

According to official disclosures, UMC already has technologies such as 2.5D silicon interposers, deep trench capacitors, wafer-to-wafer hybrid bonding, and active interposers, and has cooperated with packaging and testing plants to build a 2.5D/3D IC ecosystem. These capabilities are highly adjacent to glass packaging, because whether it is a silicon interposer or a glass interposer, RDL, copper interconnection, bonding, thinning, CMP, and subsequent packaging integration are required.

According to a report in Taiwan's *Economic Daily* on July 20, 2026, UMC is currently focusing on completing the processes after TGV, including Front-side RDL, Temporary Bonding, grinding, CMP, and glass carrier processing.

This layout conforms to UMC's capability