Who is competing for CoWoS?

If the overarching theme of the semiconductor industry over the past decade was "Moore's Law", the most prominent keyword today is undoubtedly advanced packaging.

As large language model parameters have exploded from the tens of billions scale to the trillions scale, the path of boosting computing power solely through process miniaturization is approaching its physical limits. An AI chip needs to accommodate massive computing units and high-bandwidth memory simultaneously, and traditional 2D packaging has long been unable to meet these demands. As a result, the golden combination of HBM + CoWoS has become an almost mandatory choice for all high-end AI chip manufacturers.

From NVIDIA's Blackwell architecture GPUs, to AMD's MI series accelerators, and then to cloud vendors' self-developed training chips — whoever can secure sufficient CoWoS production capacity will be able to truly establish a firm foothold in the AI computing power competition.

A "positioning battle" centered on TSMC's CoWoS packaging capacity has quietly broken out among global chip giants.

Why Is CoWoS Indispensable?

CoWoS (Chip-on-Wafer-on-Substrate) is a 2.5D advanced packaging technology developed by TSMC. In simple terms, instead of soldering chips and memory directly onto the substrate, it places computing chips such as GPUs/ASICs and HBM memory chips side by side on an interposer through high-density TSVs (Through-Silicon Vias) and micro-bumps. High-speed interconnection between chips is achieved through the dense fine wiring inside the interposer, and the entire assembly is finally packaged onto the substrate.

Image Source: The Path of Simplicity

Why go through all this extra effort? The line width of traditional PCB boards is too coarse, limiting both signal transmission distance and speed. A single GPU often needs to connect to multiple HBMs simultaneously, with bandwidth requirements reaching several terabytes per second. Only the ultra-fine wiring of a silicon interposer can handle such a massive transmission volume.

In 2011, TSMC officially launched CoWoS. After multiple rounds of iterations, it has now formed three solution categories: CoWoS-S (full silicon interposer), CoWoS-R (RDL interposer), and CoWoS-L (local silicon bridge + organic substrate). Among them, CoWoS-L is the current mainstream solution — replacing the oversized single-piece silicon interposer with a "local silicon bridge", which reduces warpage and cost while supporting larger packaging areas and more HBM stacks.

The core advantages of this architecture are very clear:

Bandwidth Enhancement: HBM and GPU are directly interconnected through the silicon interposer, delivering bandwidth dozens of times higher than traditional DDR, completely solving the "memory wall" problem in AI training;

Lower Power Consumption: Signal transmission distance is greatly shortened, significantly reducing the power consumed by data movement;

Higher Integration: Multiple Chiplet small chips + multiple HBMs can work together in the same package, breaking through the area limit of a single chip.

It can be said that without CoWoS, there would likely be no modern large-model training chips with hundreds of billions of parameters.

Who Is Competing for CoWoS Capacity?

According to Morgan Stanley's supply chain research and forecasts, the total global CoWoS wafer demand from key customers will reach approximately 1.384 million pieces in 2026, and surge to 2.682 million pieces by 2027 — nearly doubling in two years. The participants in this capacity battle have already expanded from a single GPU vendor to the entire AI computing power industry chain.

Global CoWoS Capacity Demand Forecast by Key Customers

NVIDIA: Still the Main Player, But Its Share Is Diluting

It is not hard to see that NVIDIA remains the absolute protagonist.

NVIDIA's CoWoS capacity demand will be 780 thousand pieces in 2026, jumping to 1,200 thousand pieces in 2027, firmly ranking first. From Hopper to Blackwell and the latest Rubin architecture, every generation of GPUs is deeply tied to TSMC's CoWoS-L process.

At the same time, CoWoS-R is mainly used for NVIDIA's Vera CPU production, with an expected shipment volume of 5.75 million units. Strong pre-orders indicate that Vera CPU shipments will nearly double, leading to CoWoS-R capacity demand exceeding 100 thousand pieces; CoWoS-S is used for Quantum and Spectrum switch chips.

Overall, NVIDIA alone takes up more than half of TSMC's CoWoS capacity.

However, it is worth noting that NVIDIA's share in total demand will drop from approximately 56% in 2026 to about 45% in 2027 — the absolute value is rising, but its proportional share is being diluted. This means that the CoWoS market landscape is shifting from NVIDIA's "single dominance" to a multi-player competitive environment.

AMD: The Biggest Dark Horse in 2027, Growth Nears NVIDIA

If NVIDIA is the king of existing market share, AMD is its most aggressive pursuer.

AMD's CoWoS capacity will be only 130 thousand pieces in 2026, but will skyrocket to 530 thousand pieces in 2027. Its 400 thousand piece incremental volume is almost on par with NVIDIA's (442k); the main driving force comes from the ramp-up of AMD's MI series AI server chips, as well as the large-scale adoption of 3D V-Cache and Chiplet architectures, which has more than tripled AMD's CoWoS demand in just one year (a 307% increase).

It is reported that AMD's key product in 2027 will be the MI455, with small-volume production of the MI500 (Arcadia) at the end of the year; for AMD's Venice CPU business, AMD mainly relies on non-TSMC CoWoS processes from ASE/SPIL, Amkor, etc., with capacity surging from 50 thousand pieces to 270 thousand pieces, corresponding to an expected 6.75 million CPU units, mainly driven by Agentic AI demand.

Interestingly, the 10k piece demand from AMD-acquired Xilinx remains flat, which likely indicates that all growth comes from the explosion of AMD's own product lines, and the FPGA segment's CoWoS demand appears to have saturated, or its technical roadmap has shifted to other packaging methods.

Broadcom's Network Chips Show Steady Growth

In 2026, Broadcom's capacity demand will be 300 thousand pieces, making it the second-largest CoWoS demander; in 2027, it is expected to grow to 484 thousand pieces (a 61% year-on-year increase), falling to third place after being overtaken by AMD.

Unlike the first two players, Broadcom's main product is not GPUs, but high-end network switch chips. The explosive demand for 800G and 1.6T switches in AI clusters has pushed Broadcom's Tomahawk series chips to fully adopt CoWoS advanced packaging. In addition, Broadcom is also assisting Google's TPU v7 (Ironwood) and v8i (SunFish) in chip design and manufacturing, which consumes CoWoS capacity.

MediaTek Emerges Rapidly

MediaTek's demand surges from 40 thousand pieces to 180 thousand pieces, a 350% increase. MediaTek's explosion is the most unexpected highlight on this list. This traditional mobile chip giant is aggressively expanding into the AI accelerator market, with its cloud and edge ASIC chips beginning to adopt CoWoS on a large scale, posting the fastest growth rate among all top-tier customers.

Some suppliers revealed that MediaTek's ASIC business is mainly driven by Google's TPU v8t (ZebraFish), corresponding to an expected shipment volume of 3.6 million units.

AWS: Cloud Vendor's Self-Developed Chips Ramp Up Steadily

AWS's two self-developed chip product lines (Annapurna and Alchip) have a combined demand growing from 88 thousand pieces to 126 thousand pieces, reflecting the continuous iteration of Trainium training chips and Inferentia inference chips. This demonstrates cloud vendors' determination to reduce reliance on a single GPU supplier, though their growth rate is more moderate compared to top-tier vendors.

Marvell and GUC: Custom ASIC Market Gains Momentum

Marvell's demand grows from 17 thousand pieces to 64 thousand pieces, and GUC's from 14 thousand pieces to 60 thousand pieces, representing a 276% and 329% increase respectively. The explosive growth of these two players reflects a trend: the custom AI ASIC market is booming. Marvell's DPU and AI network chips, as well as Global Unichip (GUC)'s ASIC design service business, are consuming large amounts of CoWoS capacity.

More and more internet companies are choosing to develop their own AI chips, and they all need to work with design service firms to access TSMC's packaging capacity.

Cisco: Stagnant Growth in Traditional Segments

Cisco has a relatively small scale and low growth rate, with demand only increasing from 5 thousand pieces to 6 thousand pieces, indicating that traditional network equipment and mid-to-low-end FPGAs have limited pulling power for high-end CoWoS. This segment is gradually being squeezed out by AI-related demand.

Overall, CoWoS's demand structure is undergoing profound changes:

The AI GPU Camp Serves as the Foundation: NVIDIA + AMD + Broadcom occupy the vast majority of capacity;

ASIC and Network Chips Represent New Growth: MediaTek, Marvell, and GUC benefit from demand for AI switches and high-speed interconnection chips, doubling their packaging demand and far outpacing the industry average growth rate;

Cloud Vendors' Self-Developed Chips Act as a Long-Term Variable: While their current scale is not large, cloud self-developed large-model chips continue to expand production, representing the direction of a decentralized computing power supply chain;

Traditional FPGA/Network Equipment: Xilinx and Cisco show stagnant demand, with traditional businesses having limited pulling power for high-end CoWoS.

From an industry-wide perspective, total CoWoS capacity demand from top global key customers will grow from approximately 1.384 million pieces in 2026 to 2.682 million pieces in 2027, representing an overall increase of about 94%. Global CoWoS wafer demand nearly doubles in two years, confirming Morgan Stanley's judgment of high growth in the advanced packaging segment.

When all players crowd into the same track, the problem of capacity shortage naturally emerges.

Capacity Bottleneck: TSMC Is Expanding Fast, But Not Fast Enough

TSMC, which has long recognized the strategic value of CoWoS, has been working tirelessly to expand production.

According to statistics, TSMC's CoWoS monthly capacity was only about 10 thousand wafers in 2022, and it has approached 70 thousand wafers in 2025. With TSMC and its partners actively expanding production, TSMC's CoWoS monthly capacity is expected to reach a record 120 thousand to 140 thousand wafers in 2026, further increasing to 170 thousand wafers per month in 2027 (some plans show capacity will reach 200 thousand wafers per month by the end of 2027). Production expansion is mainly concentrated in Tainan and Chiayi, with the expansion scale far exceeding previous levels.

While expanding CoWoS production, TSMC is actively promoting its industry-leading CoPoS (Chip on Panel on Substrate) panel-level packaging technology. The pilot production line is scheduled to complete commissioning in June 2026, with mass production expected as early as 2028-2029 to meet the packaging demand for large-sized chips.

Beyond TSMC, other players are also actively expanding production: by the end of 2027, non-TSMC players (ASE/SPIL, Amkor, etc.) will expand their CoWoS capacity to 80 thousand wafers per month (80kwpm). Among them, ASE/SPIL will increase from 30kwpm at the end of 2026 to 50kwpm, and Amkor will grow from 20kwpm to 30kwpm, both focusing on CoWoS-L and CoWoS-R.

It is clear that the industry supply structure is shifting from TSMC's single-point dominance to parallel capacity expansion by foundries and OSATs. UBS predicts that the industry's CoWoS monthly capacity will increase from 160 thousand wafers at the end of 2026 to 250 thousand wafers at the end of 2027, representing an annual increase of about 56%. Behind this round of expansion, Rubin, AMD Venice, Google TPU, and Amazon Trainium are simultaneously increasing their packaging demand.

At the same time, over the next five years, TSMC's CoWoS will continue to develop with larger dimensions each year to integrate more logic and HBM. In 2026, TSMC will produce the world's largest 5.5x reticle size CoWoS with a yield exceeding 98%. A subsequent 14x reticle size CoWoS integrating 20 HBMs will enter mass production in 2028, and a version capable of integrating 24 HBMs with dimensions larger than 14x reticle will be ready in 2029.

Supply chain sources reveal that not only is CoWoS demand strong, but TSMC's SoIC and CoPoS progress is also very rapid, extending order visibility in the equipment supply chain directly to 2030. For example, TSMC's SoIC capacity is also continuously expanding. Previously estimated to rise from 10 thousand to 20 thousand wafers per month in 2027, the latest news indicates this figure has been revised up to 50 thousand wafers per month, with NVIDIA taking up a large portion of that capacity.

However, new capacity will soon face an even larger pool of orders.

According to UBS calculations, total CoWoS capacity demand will grow from 1.307 million pieces in 2026 to 2.475 million pieces in 2027 (Morgan Stanley's forecast mentioned earlier is 2.682 million pieces), representing an annual increase of about 89% — significantly faster than the industry's monthly capacity growth rate during the same period.

Image Source: UBS

According to supply chain sources, the current CoWoS supply-demand gap is about 20%, which is expected to narrow to approximately 10% by the end of 2026. Other institutional calculations suggest that the capacity gap could expand to around 700 thousand pieces in 2027, exceeding 30%.

Some supply chain vendors point out that even if CoWoS monthly capacity is increased to more than 200 thousand wafers, it will still be difficult to meet all customer order demands. Combined with ongoing risks related to production expansion, monopolistic practices, and U.S.-based manufacturing, many customers that previously relied almost exclusively on TSMC have designated ASE, SPIL, Amkor, and others as recipients of overflow orders to establish a second advanced packaging supply path.

On the other hand, there are other reasons why production expansion cannot keep up with demand: first, the process threshold is