Semiconductor Equipment, New Opportunities
The sense of smell of capital always detects the industry trend first. Recently, Nearfield Instruments, a Dutch unicorn in the semiconductor metrology field, announced the completion of a Series D financing of up to $380 million, and its post - investment valuation soared to $1.6 billion. Behind it, a group of top sovereign and star capitals have gathered, including Fidelity, Temasek, Qatar Investment Authority (QIA), and Walden Catalyst.
It is worth noting that Nearfield neither engages in lithography nor traditional etching, deposition, or packaging. The reason why this rising star is highly sought after by capital is largely that it has bet on metrology and process control for future - oriented next - generation manufacturing scenarios such as High - NA EUV, GAA, CFET, and hybrid bonding.
This makes us wonder, in this mature track already divided by traditional giants, where exactly are the new opportunities in the equipment industry?
Don't worry. Let's first look at a set of data. According to the data prediction in SEMI's "300mm Wafer Fab Outlook", the global 300mm wafer fab equipment spending is expected to increase by 18% to $133 billion in 2026, then by 14% to $151 billion in 2027, continue to increase by 3% to $155 billion in 2028, and increase by another 11% to $172 billion in 2029. These increases are mainly driven by AI chips, advanced nodes, regionalized manufacturing, and storage investments. Among them, logic/microprocessors, DRAM, and 3D NAND are the major areas of equipment investment in the next few years.
This also means that the future increment will not only rely on the simple expansion of wafer fabs and the superposition of equipment quantity brought by replicating production lines; the real major change in the industry may come from the subversive reconstruction of the underlying structure and process route of chips. From the architectural evolution of GAA and CFET to the storage revolution of HBM and 3D DRAM; from the optoelectronic cross - boundary of High - NA EUV, dry photoresist, silicon photonics/CPO, etc. - it is the changes in these cutting - edge foundations that are quietly reshaping the new golden cycle of the entire semiconductor equipment industry.
Chips are accelerating towards 3D, and deposition and etching are more "in short supply" than lithography
As Moore's Law approaches the physical limit, whether it is logic, storage (DRAM/NAND), or advanced packaging, all are accelerating towards 3D development. At the 2026 VLSI Conference, this trend was very clear.
First, in the field of logic devices, the transistor architecture is transitioning from FinFET to the gate - all - around (GAA) and then to the ultimate form - the complementary field - effect transistor (CFET) architecture. At the 2026 VLSI Conference, the three global wafer manufacturing giants showed their strength: Samsung demonstrated 3D Stacked FETs, an early form of CFET, achieving a three - layer nanosheet stack of n - FET and p - FET on the same wafer with a gate pitch of 42nm; Intel demonstrated a CFET inverter with a 45nm gate pitch, combining PowerVia, back - side direct contact, and Epi - to - Epi Via, and adopting a structure with PMOS on top and NMOS at the bottom; TSMC demonstrated A16 (angstrom - scale) CMOS, introducing nanosheet transistors and Super Power Rail (SPR). Compared with the N2P process, A16 has a speed increase of 8% - 10% and a chip density increase of 8% - 10% under the same power consumption, and the mass - production time is directly set for the fourth quarter of 2026.
Samsung 3D Stacked FETs
Intel CFET inverter
TSMC A16
The same is true in the storage field. Kioxia and SanDisk introduced a roadmap for 3D NAND with more than 1000 layers at this conference. DRAM has used a planar structure for decades, but now it is following the path of NAND.
At this VLSI Conference, major giants have presented storage roadmaps to break through the 10nm physical wall: Samsung demonstrated 16 - layer vertically stacked DRAM, using GAA cell transistors, horizontal storage capacitors, and Peri - on - Cell architecture. SK Hynix demonstrated 4F² Vertical Gate DRAM, achieving more reliable read and write operations through bit - line shielding, shared back gate, wafer bonding, and die thinning.
SAIMEMORY/Intel/PSMC: Jointly demonstrated a 3D high - bandwidth DRAM using a via - in - one TSV architecture. This technology achieved an 8 - layer DRAM stack, with each layer of metal wiring directly connected to the TSV bus, making the bandwidth density reach about 0.25Tb/s/mm² and greatly improving the signal and power integrity.
The acceleration of chips towards 3D space is essentially a "paradigm shift" in semiconductor underlying processes. Equipment manufacturers have begun to re - arrange their strategies around this 3D transformation.
Applied Materials believes that although HBM and 3D stacking can improve bandwidth and energy efficiency, the manufacturing complexity has increased significantly. Currently, we observe that Applied Materials mainly has the following types of equipment to deal with 3D: 1) DRAM is no longer just a traditional storage process and is absorbing the material engineering capabilities of advanced logic. Applied Materials launched the enhanced Centura Prime Epi system on June 25, pushing the epitaxial equipment into DRAM, indicating that the competition in HBM and next - generation DDR has extended to the performance of peripheral transistors; 2) The advanced packaging Opta Quad CMP has started to serve hybrid bonding. Opta Quad can monitor the wafer status in real - time during the polishing process and dynamically adjust the process to improve in - wafer uniformity and total thickness variation control; 3) The Nokota VMax 2 copper electroplating ECD serves TSV and microbump. It can dynamically adjust the electric field to correct the uneven electroplating problem caused by layout differences; 4) PECVD is used to deal with the warping of ultra - thin DRAM dies. It mainly deposits a stress - balancing dielectric film around the TSV to improve the mechanical stability of ultra - thin DRAM dies and support 12 - layer, 16 - layer, and higher - layer HBM in the future; 5) eBeam metrology and defect re - inspection have entered advanced packaging. Applied Materials' VeritySEM 7AP provides sub - 10nm level sensitivity, targeting thick substrates, heterogeneous materials, and highly warped substrates common in HBM and chiplets; SEMVision G7AP is used for high - resolution defect re - inspection and automatic classification and has been used in the mass production of advanced packaging by leading storage and logic manufacturers.
Lam Research believes that when NAND, logic, DRAM, and advanced packaging all move towards 3D, the intensity of deposition and etching will increase significantly. In 3D NAND, this change has been fully verified. As the number of NAND layers increases, the core challenges become high - aspect - ratio channel hole etching, side - wall morphology control, thin - film stress management, and metal filling ability. Lam's Cryo 3.0 low - temperature etching technology is aimed at the high - aspect - ratio etching required for the evolution of 3D NAND to 1000 layers. Compared with traditional dielectric etching, low - temperature etching can maintain better profile control in deeper structures and improve the etching rate at the same time. This shows that in the subsequent expansion of 3D NAND, the value of etching equipment does not decrease due to the mature architecture but will continue to increase with the increase in the number of layers.
3D NAND has verified that the vertical structure will bring huge demands for etching and deposition equipment, and 3D DRAM may push the difficulty even higher. Lam said that the vertical structure of 3D DRAM may require more extreme Profile (morphology control) capabilities than 3D NAND, and currently, there is even no mature solution in the industry to meet high - yield mass production.
(Source: LAM)
TSMC's next - generation, the equipment battle for panel - level packaging CoPoS has begun
The panel - level advanced packaging technology CoPoS also brings new equipment requirements. The core logic of CoPoS technology is to completely replace the traditional circular silicon wafer with a larger rectangular glass panel as the packaging substrate. A senior person in the supply chain revealed that after moving to square panel - level packaging, the wafer output efficiency of a single substrate can soar by 5 to 6 times compared with the existing 12 - inch circular wafer. This is a brand - new packaging production line centered on the rectangular panel, completely deconstructed and rebuilt. It covers glass substrate processing, panel - level redistribution layer (RDL), ultra - large - size lithography, high - precision wafer mounting, ultra - low warpage control, and a subversive metrology mechanism.
Wei Zhejia, the chairman of TSMC, first mentioned this technology blueprint at the official level at the earnings conference in April 2026. Coupled with the recent announcement by the Taiwan Intellectual Property Office that TSMC has officially applied for the "TSMC - COPOS" trademark, all these show that TSMC regards this as the next trump card to continue Moore's Law.
Recently, TSMC's CoPoS trial production line has been quietly launched, and the first batch of trial production verification equipment has been officially moved into the Longtan Factory of VisEra, a subsidiary of TSMC. According to the equipment list disclosed by Digitimes, the initial CoPoS trial production line has carried out a strict layout in six core process areas. Equipment giants including Canon, DISCO, TEL, SCREEN, and Lam Research, as well as some emerging forces, are vying for positions in areas such as lithography and coating/development, metallization and copper electroplating, grinding/cutting and precision die bonding, wet process and high - difficulty heat treatment, and metrology.
According to a report by BigGo Finance, supply chain insiders emphasized that due to the particularity of panel - level packaging, most of the equipment required for CoPoS belongs to non - standard customized specifications, and the single - unit premium is usually significantly higher than that of traditional wafer - level equipment. Moreover, due to the shift in the process paradigm, there is a huge technological gap between it and the existing CoWoS production line. In this crucial battle, although the initial list of CoPoS includes some regular players from the CoWoS era, due to the geometric increase in R & D difficulty, the verification progress of some established suppliers has not met expectations.
For example, Lam Research's most core advantage used to be in the front - end of wafer manufacturing, such as etching. But now in TSMC's CoPoS trial production line, Lam has successfully defeated other traditional American and Japanese packaging equipment giants that had great advantages in the back - end packaging field with its latest SABRE 3D FP electroplating equipment and Quaros FP etcher.
Another example is that CoPoS introduces a glass substrate as the core medium. Although it solves the warping and miniaturization limit of traditional substrates, it brings fatal problems of fragility, transparency, and high - reflection detection. This directly leads to the infinite magnification of the status of metrology and detection in the production line. It is understood that many local equipment manufacturers in Taiwan, China, have been short - listed to achieve local substitution.
Therefore, CoPoS can be said to provide a golden opportunity for equipment manufacturers to reshuffle the cards and make a counter - attack.
Regarding the mass - production schedule, the latest news in the industry indicates that CoPoS is expected to enter the mass - production track as early as 2029, significantly earlier than the previously widely expected 2030. Some optimistic views believe that 2026 is the key verification year for equipment and materials, 2027 will enter the trial production stage, and the horn of formal mass production can be sounded in the second half of 2028. This also confirms Wei Zhejia's previous judgment: It will still take 2 to 3 years of solid progress for CoPoS to achieve large - scale production capacity.
Major changes in the photoresist route: from wet to dry
In advanced processes, the photoresist route is also changing.
In the era of below 2nm and High - NA EUV, as the circuit lines are miniaturized to the atomic level, when traditional wet photoresist (CAR) is developed and rinsed, the surface tension of water will cause the nano - lines to collapse in patches (Pattern Collapse). This physical limit is forcing the semiconductor industry to undergo a once - in - decades paradigm shift - the photoresist is comprehensively moving from the "wet era" to the "dry era".
In this field, Lam Research has made arrangements. Their Aether dry photoresist equipment and process use chemical vapor deposition (CVD) to make the photoresist "grow dry" and use plasma for dry development. According to Lam's introduction, the advantages of dry photoresist are mainly reflected in several aspects: First, metal oxide photoresist has a stronger ability to absorb EUV photons, which helps to reduce the exposure dose; second, the thin film formed by vapor deposition is more uniform, which is beneficial to improving resolution, reducing roughness, and defect rate; third, dry development reduces the risk of pattern collapse caused by liquid surface tension; fourth, it reduces the use of chemicals such as acids, alkalis, solvents, and PFAS, with certain sustainability advantages.
(Source: LAM)
Around this new route, Lam has formed a set of equipment combinations. Aether GPX is used for dry photoresist deposition, Aether GDX is used for dry development, Nimbus provides the underlying thin film, and equipment such as Gamma, G400, and G3D are used for dry photoresist removal. DV Prime, Da Vinci, EOS, and Coronus are used for wafer back - side, edge, and bevel cleaning.
It is worth mentioning that on September 15, 2025, Lam Research reached a historic comprehensive cooperation with JSR Group, a Japanese materials giant (and its MOx photoresist pioneer Inpria). The two sides buried the hatchet and withdrew all previous patent lawsuits. The two giants chose to deeply "combine