LPDDR6, the battle has begun

Papers presented by Samsung and SK Hynix at ISSCC 2026 indicate that despite the LPDDR6 standard being approved by JEDEC just a few months ago, both companies already have usable LPDDR6 chips. With technological advancements, the demand for machine learning workloads has been increasing recently, leading to an urgent need for high-capacity, high-speed memory. However, the throughput of various devices is facing bottlenecks. For small devices such as smartphones and laptops, this means that the memory subsystem is one of the biggest factors limiting the device's ability to run powerful and the latest on-chip models.

What the two companies presented at ISSCC 2026 is far more interesting than it seems on the surface. Although both Samsung and SK Hynix brought usable chips, they made very different choices in their respective design and optimization directions. Samsung adopted a more conservative speed and bandwidth strategy, sacrificing pure performance in various ways to optimize power consumption.

SK Hynix, on the other hand, utilized its latest 1-nanometer process node to directly challenge the 14.4 Gbps bandwidth ceiling specified in the JESD209-6 standard. These two papers together provide us with the first detailed and independently verified performance of LPDDR6 in actual chips rather than on paper.

Introduction to the Current LPDDR Family

LPDDR5 was initially released in 2019 with a peak data rate of 6,400 Mb/s per pin, approximately twice that of LPDDR4X. LPDDR5X followed in 2021, reaching a peak data rate of 8,533 Mb/s. Subsequently, SK Hynix increased the data rate to 9,600 Mb/s, introducing what was later known as LPDDR5T. Samsung finally went a step further, verifying the 10,700 Mb/s rate of LPDDR5X on the Dimensity 9400 platform using a 12nm process. The following table shows the generational improvements in peak data rate and single-chip bandwidth from LPDDR4X to the current LPDDR6 memory.

All previous generations (LPDDR4X to LPDDR5X) used a 16-bit channel, which means that regardless of the increase in data rate, the connection width between the memory and the processor remained the same. LPDDR6 changes it to a wider 24-bit channel, which may be more important than a simple speed increase because it means that building a unified controller capable of supporting both LP5 and LP6 modes will be very difficult.

LPDDR6 organizes its 24-bit channel into two 12-bit sub-channels per chip, which will affect the actual operation of the memory. Each 12-bit sub-channel processes its own data independently, giving the memory controller greater flexibility when processing requests and allowing for a smaller access granularity of 32 bytes per sub-channel (64 bytes for LPDDR5). For AI workloads that generate a large number of small and often irregular memory requests (rather than large sequential requests), this means that random memory access should be more efficient, thus theoretically reducing the time spent on fetching data beyond the actual needs of the workload.

For new AI workloads planned for mobile devices, the bandwidth of LPDDR5X is already insufficient, and the combination of a higher data rate and a wider bus width directly addresses this issue. Device-level AI models require the memory subsystem to be able to transfer a large amount of data quickly and stably. The transfer rate of LPDDR5X is 8,533 Mb/s (16-bit), and the peak bandwidth per chip is approximately 17 GB/s. According to SK Hynix's disclosure at ISSCC 2026, LPDDR6 can reach a peak transfer rate of 14,400 Mb/s on a wider 24-bit channel, with a maximum bandwidth of 38.4 GB/s per chip. This is about 2.25 times that of LPDDR5X and more than three times that of LPDDR5.

Before proceeding, let's first familiarize ourselves with what is specified in the JESD209-6 standard released by JEDEC last year.

The official JEDEC JESD209-6 standard defines a peak data rate of 14,400 Mb/s per pin, with entry-level products starting at 10,667 Mb/s. However, the actual situation is far more complex than just the peak data rate. As SK Hynix disclosed, the actual peak bandwidth is only 38.4 GB/s per chip, rather than the theoretical maximum of 43.2 GB/s obtained by multiplying the data rate by the bus width.

In addition to bandwidth, unlike LPDDR5X, LPDDR6 makes on-chip error correction (ECC) mandatory rather than optional. This means that error correction operations are now completed inside the memory array before the data reaches the processor. LPDDR6 also introduces the Per Row Activation Counting technology to defend against the Rowhammer vulnerability. Rowhammer is a well-known memory vulnerability where repeated access to the same memory row can cause data corruption in adjacent rows. Moreover, the new dynamic efficiency mode limits the interface to sub-channels during low-bandwidth operation, significantly improving energy efficiency, which is crucial for mobile devices.

SK Hynix's 16Gb LPDDR6 Based on the 1cnm Process

SK Hynix showcased its 16Gb LPDDR6 memory at the ISSCC exhibition, which uses the 1cnm process and is the latest generation of its 10nm-class DRAM series. The chip micrograph summary table in Figure 15.7.7 directly confirms its main performance parameters: a single-pin transfer rate of up to 14.4 Gbps and a total bandwidth of 38.4 GB/s. The chip uses two independent voltage rails: a higher voltage rail for transmitting data with extremely high speed requirements and a lower voltage rail for transmitting all other data. This is the key to SK Hynix's effective power consumption management under different operating conditions.

More precisely, the chip itself operates at two different voltage levels. The high-voltage rail VDD2C operates at 1.025V, while the low-voltage rail VDD2D operates at 0.875V. VDD2C is the critical part, which requires more power to achieve the maximum bandwidth of 14.4 Gbps per pin, while VDD2D is used for processing all other data transmissions.

SK Hynix claims that its product has an energy efficiency improvement of more than 20% compared to LPDDR5 and a higher single-channel bandwidth. By applying different voltages to different parts of the memory chip to improve energy efficiency, SK Hynix also claims that its bandwidth is three times that of LPDDR5.

The above figure more clearly shows how the dual sub-channel design operates in daily use. SC0 is the main sub-channel, running all the active logic, and SC1 is its mirror image. However, in the energy-saving mode, the entire auxiliary module is powered off, and SC0 completely controls all 32 banks. In this specific state, the single sub-channel operates at a rate of 12.8Gbps, the standby current drops to 87.3% of the normal mode, and the operating current drops to 81.1% of the normal mode. In fact, the device spends most of its time in this state, which means that these values are more important than the peak values.

SK Hynix focused on how to manage power consumption at both ends of the speed range in this report, not just the peak power consumption. The CA (Command and Address) bus in LPDDR6 is responsible for telling the memory what operations to perform and where to perform them. Its operating frequency ranges from 1.6 GHz to 3.6 GHz, approximately three times that of LPDDR5 (as pointed out by SK Hynix), which poses a real challenge to multi-level configurations (i.e., multiple chips sharing CA pins).

To solve this problem, SK Hynix divides the operating frequency range into three bands, each equipped with an independent buffer, and selectively activates these buffers according to the operating conditions. Combined with a fast CS control scheme (which can more efficiently control the CA signal path during low-speed operation), the low-frequency standby current is reduced by 42%, and the medium-frequency standby current is reduced by 19%. For a device that spends most of its time in an idle state, this is the real key to energy saving.

The Shmoo diagram in the above figure shows the power consumption and voltage targets set by SK Hynix for this data rate. For those unfamiliar with the Shmoo diagram, it is a graph that visually represents the qualified and unqualified performance of a chip under different voltages and clock frequencies. This allows us to more clearly understand the actual operating range of the chip and whether it has reached its performance limit. At VDD2C of 1.025V, SK Hynix's device can meet the qualified standard of 14.4 Gbps, which is also the upper limit of JEDEC.

Reducing the voltage to 0.950V will cause the bandwidth to drop back to 10.9 Gbps. This indicates that SK Hynix's 1cnm process requires an additional voltage margin to operate reliably at peak speed without performance degradation. Without this margin, the performance will drop sharply. This is SK Hynix's first-generation LPDDR6 memory, and this situation is not uncommon for a new process node, but it is very different from Samsung's approach. Samsung chose to sacrifice bandwidth in exchange for higher energy efficiency.

This relationship between voltage and speed becomes particularly important when we directly compare it with what Samsung presented in its paper because the two companies made very clear differences in optimization, and their respective shmoo diagrams also reflect this.

Samsung's 16Gb LPDDR6 with a Speed of 12.8 Gbps

Samsung released its latest product at ISSCC 2026, a 16Gb LPDDR6 device manufactured based on a 10nm-class DRAM process. The summary table in Figure 15.8.7 and the following table directly confirm its key specifications.

The 12.8 Gbps bandwidth announced by Samsung is not like SK Hynix's pursuit of the peak bandwidth of 14.4 Gbps. The paper describes 12.8 Gbps as the lowest voltage operating point specified by JEDEC, which indicates that Samsung ultimately chose to focus the engineering of its first-generation product on energy efficiency.

The power domain division shown in the above figure is the key to Samsung achieving its efficiency goal. Instead of running all circuits under a single voltage, Samsung allocates them to two different power rails according to the speed requirements of the circuits. Circuits with high speed requirements are connected to VDD2C, while peripheral circuits and non-critical circuits are connected to VDD2D, which operate at 1.0 V and 0.875 V respectively.

The bar chart in the figure clearly shows the results: the read power consumption is reduced to 73% of LPDDR5X, and the write power consumption is reduced to 78% of LPDDR5X. The DQ pins are the physical connections on the memory chip, responsible for transmitting data between the memory and the processor. At high speeds, the states of these pins switch rapidly, and power is consumed every time the pin state changes from 0 to 1 or from 1 to 0. Samsung also extended the power gating technology to the high-frequency DQ (data I/O) pins and claims that this can additionally reduce the standby power consumption by 10%.

Samsung also implemented Per Row Activation Counting (PRAC), which is Samsung's deterministic solution to the Rowhammer vulnerability. Instead of simply relying on a probabilistic refresh mechanism, PRAC directly embeds a counter into the memory array, tracks the activation of each row word by word, and triggers mitigation measures before actually reaching the attack threshold. The bar chart in the above figure shows the results: compared with LPDDR5X, LPDDR6 with PRAC requires approximately five times the number of attacks to trigger mitigation measures. For a standard that is increasingly expanding into the automotive and edge artificial intelligence fields, the importance of this deterministic protection is far greater than in the pure smartphone application scenario.

Samsung's Shmoo chart in the above figure highlights what the voltage selection implies: it is mainly optimized for energy efficiency rather than raw bandwidth. By carefully observing the Shmoo chart, Samsung's LPDDR6 can reach a bandwidth of 12.8Gbps at a voltage of 0.97V, which indicates that the performance of the chip has not reached its limit.

Comparison of SK Hynix's and Samsung's Solutions

The energy efficiency of Samsung's and SK Hynix's respective LPDDR6 design solutions cannot be directly compared. SK Hynix claims that its overall energy efficiency is 20% higher than that of LPDDR5, while Samsung says that its read performance is 27% higher than that of LPDDR5X, and its