Tao's Law: Can a chip giant be created?

On May 25th, a speech and a signed paper by He Tingbo, the president of Huawei's Semiconductor Business Department, set off a storm in China's chip industry.

In this appearance, He summarized Huawei's six - year chip - making experience into a paper and a theory and presented it all.

During these years of being blocked by advanced process technologies, Huawei's semiconductor team has mass - produced 361 chips and confirmed a conclusion in these chips:

Merely relying on "geometric scaling" by reducing the transistor size to increase transistor density and chip performance has approached the physical and cost limits;

"Time scaling" by reducing the time constant τ and performing logical folding on the chip is becoming a new chip design path to bypass the extreme process dependence.

This is the "Tao's Law" proposed by Huawei to replace Moore's Law in the field of chip design.

Based on this law, He Tingbo pointed out that by 2031, the transistor density of high - end chips based on this route is expected to reach the level equivalent to the 1.4 - nanometer process.

It should be noted that even TSMC and Intel's 1.4 - nanometer process will not enter the mass - production stage until 2029.

01

The End of Moore's Law

On April 19, 1965, the American magazine "Electronics" published an article titled "Cramming More Components onto Integrated Circuits" by Gordon Moore, the then - director of the Research and Development Laboratory at Fairchild Semiconductor.

In this short article of only four and a half pages, Gordon Moore put forward his observation:

Since the advent of integrated circuits in 1959, the number of components on integrated circuits has approximately doubled every year. Meanwhile, he also predicted that this trend would continue for at least the next decade.

This observation later became the well - known Moore's Law, which was revised by Moore himself in 1975 to "double every two years".

Moore's Law has been the "industry contract" of the global semiconductor industry for a long time and has driven the greatest technological explosion in human history:

From personal computers to smartphones, from the Internet to artificial intelligence, computing power has increased exponentially while the cost has continued to decline.

In 1974, IBM scientist Robert Dennard and others published a paper proposing the Dennard Scaling Theory.

This theory states that as the transistor size is scaled down proportionally, the voltage and current also decrease proportionally, and a constant electric field can be maintained, thus keeping the power density constant.

This theory perfectly fits Moore's Law, which was already popular at that time: while the number of transistors increases exponentially, the performance/power ratio and performance/cost ratio also increase synchronously.

With the support of this theory, architectures such as FinFET and Gate - All - Around (GAA) have further extended this golden era.

However, cracks began to appear in this "industry contract" in the early 21st century.

Around 2005, the Dennard Scaling first failed. As the chip feature size entered below 90nm, the thinning of the gate insulating layer of traditional silicon dioxide led to a sharp increase in quantum tunneling leakage current, and the voltage could no longer be reduced proportionally. The "Dark Silicon" phenomenon emerged - more and more transistors on the chip could not work simultaneously due to power consumption limitations.

The clock frequency has since stagnated, and the multi - core architecture has become the mainstream.

After that, when it comes to the performance of smartphones and laptops, the number of CPU cores, the number of large and small cores are increasingly mentioned, which has indirectly become an important parameter for measuring CPU performance, precisely for this reason.

However, the geometric scaling (pure dimensional shrinkage) did not collapse instantly but experienced multiple challenges and reversals. Behind the reversals, companies such as Intel continuously upgraded through technologies such as EUV lithography and FinFET, pushing the chip process nodes to 7nm, 5nm, and even more advanced processes.

Just this year, the launch of the 18A process technology (1.8nm) has given Intel, which had been overtaken by NVIDIA and AMD, a new boost.

But after entering the 7nm node, some subtle things began to happen:

The returns brought by the chip process technology began to decline sharply:

The speed saturation reduced the improvement of the channel length on the delay from quadratic to linear;

The local interconnection parasitic RC dominated the delay;

The depreciation cost of masks and EUV equipment soared, raising the chip design budget for the 2nm node to over $1 billion;

The cost per transistor no longer decreased, and even increased at some advanced nodes;

...

Due to the emergence of this series of phenomena, after 2010, many industry leaders publicly admitted the slowdown of Moore's Law.

In this process, we can see that Intel took five years instead of two to move from 14nm to 10nm, breaking its "pendulum strategy", and the International Roadmap for Devices and Systems (IRDS) gradually diluted the traditional predictions based on Moore's Law.

In fact, Gordon Moore himself predicted as early as 2003 that "no exponential growth can last forever".

By around 2020, the "industry contract" of pure geometric scaling was actually no longer sustainable.

The end of Moore's Law is not a sudden death but a gradual decline process, which marks the transition of the semiconductor industry from the "easy era" to the "difficult era":

Under the squeeze of physical limits (atomic scale, quantum effects), economic limits (astronomical investment), and application limits (diminishing performance returns), the traditional "node - chasing" model is no longer sustainable, and the entire computing stack urgently needs new optimization goals.

02

Tao's Law and Huawei's Six - Year Chip - Making Journey

On October 10, 2018, at the Huawei Connect Conference in Shanghai, Xu Zhijun, the rotating chairman of Huawei, officially announced Huawei's full - stack and full - scenario AI strategy.

During this period, Huawei's internal artificial intelligence project codenamed "Da Vinci", which had been speculated by the industry, also made its official debut.

The so - called "Da Vinci" project is actually a chip architecture researched by Huawei. This architecture adopts a heterogeneous design of 3D Cube matrix computing units, vector units, and scalar units, supports mixed - precision computing, and precisely matches the neural network data flow.

Along with the Da Vinci project, Huawei also unveiled its first batch of self - developed AI chips for the artificial intelligence field based on the Da Vinci architecture - Ascend 910 (for training) and Ascend 310 (for inference).

According to the official data provided by Huawei at that time, the single - chip FP16 computing power of Ascend 910 reaches 256 TFLOPS, leading the industry in computing density.

This was an important milestone in Huawei's "chip - making" strategy, but greater challenges followed.

In May 2019, the United States added Huawei to the Entity List, and further tightened export controls in 2020. Since then, Huawei has been cut off from the supply of global advanced processes, and Huawei's semiconductor team has embarked on a six - year long - march.

Under extreme pressure, from 2020 to 2026, Huawei's semiconductor team designed and mass - produced 381 chips, covering fields such as mobile, AI, automotive, and infrastructure.

Facing the limitation of advanced lithography technology, they shifted the optimization goal from "geometric scaling" to time scaling (τ scaling) - that is, systematically reducing the single - feature time constant τ, from picosecond - level transistors to second - level system workloads.

On May 25, 2026, at the IEEE ISCAS conference, He Tingbo officially proposed Tao's Law (τ Scaling Law), suggesting using time rather than transistor area as the main optimization indicator.

It is worth mentioning that as a veteran in Huawei's chip field for 20 years, He Tingbo has held various positions in the chip business (development, research, architecture, supply chain), served as the R & D minister, the president of HiSilicon, and the president of the 2012 Laboratory since joining Huawei in 1996. She is currently the director of the Scientists' Committee, the director of ITMT, and the president of the Semiconductor Business Department.

She pointed out:

Merely relying on "geometric scaling" by reducing the transistor size to increase transistor density and chip performance has approached the physical and cost limits;

"Time scaling" by reducing the time constant τ and performing logical folding (LogicFolding) on the chip is becoming a new chip design path to bypass the extreme process dependence.

Tao's Theory has since become another shared optimization goal across the entire computing stack after the Dennard Scaling Theory.

According to the technical analysis provided by He Tingbo:

In the field of mobile SoCs, the LogicFolding technology has become a key breakthrough: Partitioning digital, analog, and memory circuits into vertically stacked active layers, shortening the critical path line length through ultra - fine pitch hybrid bonding, and reducing parasitic RC.

At a fixed device node, Kirin 2026 increased the transistor density from 155 to 238 MTr/mm² (a 55% increase), improved the SoC performance and energy efficiency by 41%, and increased the frequency by 13%.

In the future, through multi - layer folding, the density is expected to further increase by 2035.

At the AI system level, the Unified Bus (memory semantic unified bus) reduced the remote access delay from tens of microseconds to about 100ns (a reduction of about 500 times); the near - package Hi - ONE optical I/O and 3D Folding solved the N² - vs - N fan - out dilemma, expanding the memory bandwidth, I/O, and power delivery from the perimeter to the surface, achieving an N² scale synchronous with the computing power.

By 2035, the integration of AI hardware is expected to increase by more than 100 times.

In addition, Huawei has also set an advanced chip development goal for itself based on this law:

By 2031, the transistor density of high - end chips based on this route is expected to reach the level equivalent to the 1.4 - nanometer process.

Although Huawei's chip - making is no longer a secret in the industry, and Huawei has previously revealed some concepts of heterogeneous computing, software - hardware collaboration, and algorithm - defined chips, the proposal and announcement of Tao's Law still caused a great stir in the industry.

03

Can China Cultivate a Global Chip Giant?

After being restricted by advanced processes, the development of domestic chips has been attracting global attention.

In the era of global industrial division of labor, without the collaboration of the global supply chain, can China produce a chip giant that can compete with NVIDIA, Intel, AMD, etc.? This is one of the hottest questions in the global chip industry.

In fact, after the new artificial intelligence paradigm such as large models has detonated the demand for computing power, the global computing power industry is also undergoing a reshaping. Global technology giants have started to develop their own chips, and the chip industry chain is seeking a new paradigm in the post - Moore's Law era. At this time, China's chip industry has quietly completed a bottom - up reshaping.

What we can see is that the domestic chip industry is gradually making up for its shortcomings in design, manufacturing, packaging, and testing, and a group of leading enterprises are stepping into the spotlight.

Firstly, domestic leading wafer manufacturers have mastered the 7nm process technology, and the production and manufacturing of 7nm domestic chips have become mature and stable;

Secondly, a group of GPU manufacturers in China, including Cambricon and the "Four GPU Dragons", have begun to grow, becoming an important force in the domestic AI computing power ecosystem;

In addition, technology giants such as Huawei, Alibaba, and Baidu have invested heavily in self - developed chips and started to follow the software - hardware collaboration route similar to Apple, which has further coordinated models, algorithms, and chips.