Niuxin's domestic advanced process DDR5/LPDDR5 IPs have both achieved a breakthrough of 6400Mbps.
With the rapid development of large AI models and intelligent driving, the volume of data is growing rapidly, and the system's demand for data throughput capacity continues to rise. Although many computing power chips have extremely high theoretical computing power, they often struggle to fully realize their actual performance due to limited data transmission bandwidth. This bottleneck caused by the mismatch between storage and computing speeds has made high-speed storage interface IP a crucial battlefield for unleashing the actual performance of chips.
Niuxin Semiconductor has developed DDR5/LPDDR5 IP based on domestic advanced processes, and both have successfully achieved high-performance verification at 6400Mbps. It's worth noting that although Niuxin had previously achieved a measured rate of up to 8400Mbps for DDR5 IP on a more advanced process node, it was still able to push the rate to 6400Mbps on the domestic advanced process this time, fully demonstrating the company's core strength in compensating for the process gap through architecture and circuit design innovation. With the combined advantages of "high performance + low cost + supply chain security", Niuxin provides customers with a new differentiated path.
Breaking through process bottlenecks: High-speed design innovation under domestic advanced processes
Achieving an ultra-high rate of 6400Mbps for DDR5/LPDDR5 IP on domestic advanced process nodes is much more difficult than achieving the same rate on more advanced processes.
From the perspective of semiconductor physics at the underlying level, there are mainly three core contradictions:
Firstly, there is a contradiction between the transistor driving ability and the signal swing. The intrinsic speed of transistors in this domestic advanced process is slow, and the driving ability is weak. To ensure a clear and open signal eye diagram at the same high speed, a larger voltage swing is often required, but this leads to a sharp increase in power consumption and thermal density.
Secondly, there is a contradiction between timing accuracy and process deviation. 6400Mbps means that the unit data interval is only 312.5 picoseconds. Completing accurate sampling within such a narrow window places sub-picosecond requirements on clock jitter and skew. The inherent device mismatch and voltage drop fluctuations in this domestic advanced process can easily erode the already meager timing margin.
Finally, there is a contradiction between signal integrity and the parallel bus bit width. In a high-speed parallel DDR interface, the simultaneous flipping of dozens of data lines can cause severe simultaneous switching noise, interfering with adjacent signals. Inter-symbol interference causes adjacent bits to "contaminate" each other, and the problem becomes more prominent as the frequency increases and the bit width widens.
Facing these challenges, Niuxin Semiconductor has achieved engineering breakthroughs through systematic innovation of multiple core technologies. As an IP provider in China with self-developed PHY and controller, two core modules, Niuxin has significant advantages in the integrated closed-loop scheduling of the DDR controller and PHY. Through the advanced arbitration mechanism of its self-developed DDR controller and the scheduling of a 64-entry deep command queue, combined with the low-power strategy of its self-developed PHY, Niuxin has achieved integrated and coordinated optimization of performance, power consumption, and latency. This solution supports multiple energy-saving modes, including doze, light, and deep sleep, and can be flexibly adapted to different scenarios such as AI training, real-time inference, and standby sleep.
Meanwhile, in the fast frequency switching technology, Niuxin supports up to 8 fast switching frequencies, and the switching time is less than 5 microseconds. This ability allows the chip to adjust the operating frequency instantaneously according to the real-time load, maximizing the average energy efficiency while ensuring peak performance, which is particularly crucial for battery-powered mobile devices and edge inference scenarios.
Connecting domestic links: Progress in actual measurement verification and ecological compatibility
The ultimate test of technological breakthroughs comes from the results of actual silicon verification and the customer adoption process.
In terms of core indicators, Niuxin's DDR5 IP has achieved a stable rate of 6400Mbps under the domestic advanced process and supports the latest DFI 5.1 standard interface; the LPDDR5 IP also reaches 6400Mbps, and the system bandwidth is also 51.2GB/s at a 64-bit bit width. Compared with the product indicators of international mainstream manufacturers at the same process node, Niuxin has reached the same or better level in key dimensions such as data rate, interface version, and frequency switching flexibility.
LPDDR5 6400Mbps eye diagram
The breakthrough in ecological compatibility is also of great significance. This IP solution has been fully adapted to domestic DDR5/LPDDR5 memory particles, truly connecting the fully domesticated link from the interface IP to the physical particles, and from the design tools to the manufacturing process. This means that customers can complete the full system design verification and mass production adoption without relying on specific overseas memory particle brands, greatly improving the degree of self-control of the supply chain.
Currently, Niuxin has several important partners that have made key milestone progress in project verification. This IP solution performs outstandingly in terms of environmental robustness, supporting a junction temperature range from -40°C to 125°C, and the ESD human body model protection reaches 2000V, meeting the strict environmental requirements of all scenarios from air-cooled cabinets in data centers to high-temperature cabins in vehicles. Whether it is continuous high-temperature operation inside a server chassis or severe temperature changes near a car engine compartment, this IP can maintain stable signal quality and bit error rate performance.
Reconstructing the competition logic: The commercial value of balancing cost and security
In the context where the cost of advanced process tape-out can easily reach hundreds of millions of dollars and the production capacity is restricted by geopolitical factors, Niuxin's high-performance IP solution based on domestic advanced processes brings quantifiable comprehensive value to customers.
In terms of yield, public data shows that after years of refinement, the defect density of this domestic advanced process is much lower than that of newly introduced more advanced process nodes, and the mass production yield is usually 10% - 20% higher. This means that Niuxin's IP solution can help customers significantly reduce costs in the entire chain of wafer manufacturing, packaging, and testing. For terminal chips with an annual shipment of tens of millions, reducing the cost per chip by a few dollars can bring tens of millions of dollars in economic benefits. Additionally, a higher yield means a shorter shipment cycle and more stable production capacity ramp-up ability, which helps to seize the market opportunity.
In terms of supply chain security, in the current international competitive environment, the intellectual property barriers of more advanced process nodes are high, and there is uncertainty in production capacity allocation. Niuxin's solution is based on the domestic controllable advanced process production capacity resources and the domestic memory particle ecosystem, providing customers with a completely self-controllable supply guarantee system, which can effectively avoid the risk of supply interruption caused by geopolitical factors. For critical infrastructure chips such as servers, base stations, and automobiles that require long-term and stable supply, the value of this "supply chain resilience" is more important than simple technical indicators.
This IP solution has clearly focused on three typical application scenarios. In the field of AI servers and intelligent computing centers, the demand for memory bandwidth in large model training is growing exponentially. Integrating 32 IP instances on a single chip can support TB-level memory bandwidth, directly addressing the "transport capacity" bottleneck in AI training. This solution has been verified in multiple domestic high-end server chip projects. In the field of intelligent driving domain controllers, on-vehicle central supercomputers require high-bandwidth, low-power memory to support multi-sensor fusion and real-time decision-making. Niuxin provides a self-developed memory interface solution for domestic intelligent driving chips. In the field of edge computing and high-end embedded systems, the LPDDR5 IP combines multi-level low-power modes at a high speed of 6400Mbps and is equipped with fast frequency switching ability, which can perfectly adapt to scenarios such as edge inference and industrial vision that have extreme requirements for energy efficiency.
In the current context of continuously increasing computing power demand, relying on the most advanced processes is no longer the only way to improve system performance. Niuxin Semiconductor is rooted in domestic advanced processes and, through systematic circuit and architecture innovation, has proven that this node can also support the high-performance requirements of high-speed storage interfaces. This approach of compensating for the process gap through in-depth design not only reduces the overall cost and supply chain risk of chip development but also provides the industry with a practical development path that focuses on system value and gets rid of process anxiety. The significance of technological breakthroughs is always reflected in creating quantifiable commercial returns for customers.
This article is from the WeChat official account "Niuxin Semiconductor". The author is Niuxin Semiconductor. It is published by 36Kr with authorization.