Chip manufacturing, a new competition
Currently, the shortage of wafer fab capacity has become a consensus. Driven by AI, global infrastructure manufacturers are also "scrambling" for chips, which has triggered a wave of chip capacity expansion.
In April 2026, TSMC, the world's largest semiconductor foundry, stated, "It is expected that the capital expenditure in 2026 will reach approximately $56 billion. We will focus on investing in capacity expansion to meet the needs of AI - related customers such as NVIDIA, AMD, and Apple." However, the company did not deny that even with the increased capital expenditure, it would still be insufficient to meet the demand in 2027.
At the company's first - quarter earnings conference call in April 2026, CEO C.C. Wei said, "It takes two to three years to build a new factory, and there is no shortcut. Further expanding the production scale will take another one to two years."
On the surface, the capacity mentioned by C.C. Wei seems to focus on wafer manufacturing. However, from the market feedback, the expansion of advanced packaging is also progressing rapidly globally.
Advanced Manufacturing: Leading the Capacity Expansion
In this wave of capacity expansion, wafer fabs are undoubtedly at the forefront, and TSMC is the leader among them.
According to previous reports, the company plans to accelerate the construction of new factories in Japan, Taiwan, and the United States to produce 3 - nanometer chips. The Taiwan factory is expected to start production in the first half of 2027, the US factory in the second half of the same year, and the Japanese factory in 2028.
The company also plans to expand its production scale using the 3 - nanometer process node, which the company established in the past few years. In the field of 3 - nanometer process technology, the company has no competitors.
C.C. Wei said, "Previously, once the capacity of a certain process node reached the target, we would not increase the capacity anymore. However, we are now implementing a plan to expand capacity globally to meet the strong demand for 3nm technology in the next few years. Application areas include smartphones, high - performance computing AI (including high - performance computing and AI based on high - bandwidth memory [HBM] chips), automobiles, and the Internet of Things."
TSMC, with its most advanced 2 - nanometer chips, started mass production before the end of 2025, leading competitors such as Samsung Electronics and Intel and driving the industry forward. However, according to Handel Jones, CEO of International Business Strategies, TSMC's competitors are also continuously improving their competitiveness.
With its strong financial resources in the memory and logic chip business and its own - brand consumer electronics business, Samsung enjoys economies of scale. Since the beginning of 2026, the profits of Samsung's memory business have also continued to grow. According to Jones' prediction, by 2026, Samsung's memory sales are expected to exceed $200 billion, and the operating profit will exceed $120 billion.
Samsung is also catching up in process technology.
It is reported that Samsung's 'SF2P' (second - generation 2nm process) is gradually competing with 'N2' (TSMC's 2nm process) in terms of power consumption, performance, and area (PPA). The company has obtained many large customers, and ultimately its capacity will reach the limit.
Samsung, the world's second - largest wafer foundry, is expected to more than double the capacity of its factory in Austin, Texas, and increase the monthly wafer production to 50,000 pieces. In addition, the company is also adding a monthly capacity of 20,000 wafers in South Korea and expanding the internal consumption of its 2 - nanometer wafers.
In addition, Intel has joined hands with Elon Musk to build TeraFab. The Terafab project - with the goal of providing 1 terawatt of computing power per year - is Musk's latest ambitious plan. Although Tesla designs its own autonomous driving FSD chips, Musk's company has never produced semiconductors. However, he now plans to produce semiconductors on a scale far exceeding the world's existing capacity. First, a pilot production line will be established in Austin, using Tesla's existing electric vehicle factories and infrastructure.
The idea is that these chips will be used to support Musk's artificial intelligence (AI) business, xAI, including a series of humanoid robots and space data centers - many in the semiconductor industry are not optimistic about these ambitions. The final scale of the project and whether it will expand to multiple locations outside Texas are currently unclear.
According to Bloomberg, Elon Musk's assistants have contacted suppliers in the chip industry, including Applied Materials, Tokyo Electron Limited, and Lam Research, to prepare for his envisioned Terafab project. This is an early step in his bold attempt to enter the cutting - edge chip production field and may face arduous challenges.
According to people familiar with the matter, employees of the joint venture between Tesla and SpaceX have been inquiring about the prices and delivery times of various chip - manufacturing equipment. These people, who wished to remain anonymous, said that in the past few weeks, they have contacted manufacturers of photomasks, substrates, etching machines, deposition machines, cleaning equipment, testers, and other tools.
The Terafab team also sought support from chip - manufacturing partner Samsung Electronics. However, according to people familiar with the matter, the South Korean company proposed allocating more capacity to Tesla in its planned factory in Taylor, Texas.
Advanced Packaging: Catching Up
As mentioned above, while advanced manufacturing is accelerating, advanced packaging, as the new savior of Moore's Law, is also advancing simultaneously. TSMC is also the main player in this regard.
In mid - April, there were reports that in response to the rapid growth of AI applications in the Apple and non - Apple camps, TSMC is fully building its first advanced packaging factory (AP9) in the United States, which will start producing InFo and CoWoS in 2028. In Taiwan, the expansion of SoIC capacity will be accelerated, and it is expected to reach a monthly production of 40,000 pieces in 2027.
As mentioned above, TSMC has announced that its capital expenditure this year will range from $52 billion to $56 billion, challenging a new high with a year - on - year growth rate of about 27%. Among them, about 70% to 80% will be used for advanced process technologies, about 10% to 20% for advanced packaging, testing, photomask production, and other projects, and the remaining 10% for special process technologies, indicating that advanced packaging is a major focus this year. Meanwhile, there are reports that Samsung Electronics plans to invest $4 billion to build a chip packaging factory in Thai Nguyen Province in northern Vietnam. The factory will be built in phases, with the first - phase investment of $2 billion.
In addition to these two major players, Intel is also becoming a new winner in the packaging market with EMIB.
At the quarterly earnings conference call in January, Intel CEO Pat Gelsinger claimed that Intel's packaging technology is a "huge differentiating advantage" from its competitors. CFO Dave Zinsner said at the same meeting that the company expects the revenue from the packaging business to be "realized even before the wafer business revenue starts to have a substantial impact." Zinsner said that in the past 12 to 18 months, he has raised the revenue forecast for the packaging business from hundreds of millions of dollars to "well over $1 billion."
Zinsner elaborated on this at the Morgan Stanley Technology, Media, and Telecom Conference in March. He said that Intel's packaging business "ironically has become the most interesting part of the current foundry business" and added that the company "is about to complete some packaging revenue deals worth billions of dollars per year."
In addition to these wafer fabs, traditional packaging giants are also vigorously expanding their advanced packaging capacity.
First, let's look at ASE, the packaging leader. According to Wu Tianyu, the CEO of the holding company, 2026 will see the largest - scale factory - building wave in the company's history, with six new factories starting construction simultaneously around the world, located across Kaohsiung in Taiwan, the United States, Malaysia, Japan, Germany, and Mexico. Among them, the investment in the Renwu base in Kaohsiung exceeds NT$100 billion, focusing on high - end testing and advanced packaging capacity. Facing the supply - chain restructuring caused by geopolitics, ASE has adopted a global layout strategy. It has not only completed a testing base in California, the United States, but also expanded Factory 5 in Penang, Malaysia, to strengthen its packaging and testing capabilities in Southeast Asia. This move aims to meet the strong demand brought by AI and high - performance computing (HPC) and ensure the resilience of the supply chain under regional political fluctuations to meet the strict requirements of global customers for "localized production."
JCET, from the Chinese mainland, also pointed out in a recent investor communication when talking about the next - step capacity expansion plan that the company will continue to focus on the layout of high - end capacity based on its market judgment and will focus on the following aspects: First, tilt towards application areas. Based on future market forecasts, it will moderately focus on areas such as automotive electronics, computing storage, and high - density power supplies. Second, deepen customer cooperation. It will always attach importance to customer relationships and continuously strengthen the binding with leading high - end customers. Third, increase R & D investment. It will focus on breakthroughs in advanced packaging technologies and cutting - edge fields to promote the in - depth integration of technology development and application requirements. Overall, considering the current strong demand trend for advanced packaging, the company will continue to increase relevant investment.
Yongsi Electronics also pointed out in a transcript of an investor communication that the company's capital expenditure in 2026 is expected to increase compared with 2025, mainly in areas such as expanding the capacity of existing product lines, introducing new customer products, wafer - level packaging, 2.5D, and FC - type products.
Recently listed on the capital market, Shenghe Jingwei is steadily extending its back - end advanced packaging capabilities based on its advantages in mid - stage silicon wafer processing technology. The company also disclosed in its IPO prospectus that it will use the raised funds for the "Three - Dimensional Multi - Chip Integrated Packaging Project" and the "Ultra - High - Density Interconnect Three - Dimensional Multi - Chip Integrated Packaging Project." The implementation of these two projects will further strengthen Shenghe Jingwei's one - stop service capabilities in the field of chiplet multi - chip integrated packaging and testing and consolidate its leading position in the industry.
In short, the competition in advanced packaging is taking place globally.
Storage Manufacturers: Emerging Forces
In this wave of chip capacity expansion, storage chip manufacturers are an emerging representative. On the one hand, they are expanding chip production, and on the other hand, they are also expanding advanced packaging production.
According to South Korean media reports, this year, Samsung will give priority to transforming the production line in its Pyeongtaek complex in Gyeonggi Province into storage chip production and accelerate the construction of new facilities in this complex.
At the P4 factory, the company is upgrading its dynamic random - access memory (DRAM) production line to the latest 1c process, which will be used to produce high - bandwidth memory (HBM) and advanced DRAM chips. Samsung's goal is to achieve a monthly capacity of over 200,000 wafers using the 1c process by the end of the year through production line transformation and new equipment installation.
The construction of the P5 factory, which was postponed due to the downturn in the semiconductor industry, has resumed this year, about six months ahead of the original schedule. The chip manufacturer is recruiting tens of thousands of new workers to build this giant wafer factory capable of producing HBM, DRAM, NAND flash memory, and potential foundry chips. The factory is expected to be completed in the first half of 2027, and equipment installation will start later, with the goal of achieving mass production in the second half of 2028.
The construction of the last factory in Pyeongtaek, P6, is expected to start in the third quarter of 2028. SK Hynix is currently focusing on short - term investment to expand the M15X factory in Cheongju, North Chungcheong Province, while upgrading its old production lines.
The company is adding 1b DRAM capacity at the M15X factory and accelerating the conversion of the 1c process at the M14 and M16 factories to produce HBM and server DRAM. Last year, the capacity of the M15X factory reached 10,000 wafers per month, and it is expected to increase to 70,000 wafers per month this year.
In terms of new projects, SK Hynix is promoting the construction of a semiconductor industrial cluster in Yongin, Gyeonggi Province, which is one of the largest semiconductor manufacturing projects in the world. The cluster will ultimately accommodate six factories of Samsung and four factories of SK Hynix, with the construction of SK Hynix's factories being promoted first.
The construction of the first wafer factory, Y1, is expected to be completed in February next year, ahead of the original plan. Equipment installation is scheduled to start in the second quarter of 2027. Y1 will be built in six "phases" of clean rooms, which are units used for capacity expansion in wafer factory construction. Each phase will increase the building area and related equipment to expand the wafer capacity. The first three phases are expected to be put into operation in the same year, with a monthly capacity of 150,000 wafers. After the remaining phases are fully put into operation, an additional 150,000 wafers of monthly capacity will be added.
The construction of the second wafer factory, Y2, in this industrial cluster is expected to start around the third quarter of 2028.
In terms of packaging, the popularity of HBM and other products has made them look for new growth opportunities.
According to the business section of The Herald on Tuesday, SK Hynix recently started pile - driving construction at its site in Indiana, marking the official start of the foundation construction of an advanced packaging factory focusing on artificial intelligence. The foundation work is expected to last for several months, and ground construction may start in the second half of this year.
This project is part of SK Hynix's plan to invest $3.87 billion in 2024 to build this 56 - hectare factory. It is expected to start mass production in the second half of 2028, focusing on the production of next - generation high - bandwidth memory products such as HBM4E and HBM5.
Meanwhile, SK Hynix is also accelerating domestic investment. The company is building an advanced packaging factory worth 19 trillion won (about $12.9 billion) in Cheongju, which is expected to be completed in 2027.
Meanwhile, Samsung Electronics is reshaping the competitive landscape of the high - bandwidth memory (HBM) back - end process. The company plans to build a new eight - story semiconductor wafer factory covering an area of 8,870 pyeong in its factory in Onsan, South Chungcheong Province, and simultaneously build back - end process and packaging production lines. This move is interpreted as Samsung's attempt to upgrade its Onsan factory, which was previously focused on testing, into a comprehensive back - end production base for HBM, thereby ensuring yield, delivery time, and customer response speed.
According to industry insiders on the 21st, Samsung Electronics is planning to build a new wafer factory dedicated to semiconductor back - end processing in its Onsan factory. The building is expected to be four to eight stories high and will accommodate a back - end processing production line centered around the white - panel (WP) line and a packaging production line. This is interpreted as the discussion on expanding the HBM back - end processing capacity of Samsung Electronics' Onsan factory has gone beyond the evaluation stage and entered the stage of specific facility configuration.
The key to this wafer factory lies in the process configuration. It is reported that Samsung Electronics is committed to establishing a back - end process line centered around the wafer test line (WP line) and building a packaging (PKG) line. The wafer test line is used to verify the electrical characteristics and defects of chips in the wafer state, while the packaging line is the stage of stacking and packaging chips to complete the final product.
Integrating these two functions in the same space can immediately reflect the test results in the packaging, thereby improving both production efficiency and quality response speed. Industry insiders believe that for products such as HBM, this integrated operation architecture is more critical because the stacking structure, thermal control, and packaging accuracy directly determine the performance and yield of the product.
It should be noted that the capacity expansion mentioned above is only part of what we have observed and does not represent the entire industry. However, we can be sure that in the current context of continuously rising AI demand, a new competition around chip capacity has already begun.