Transistors of 0.7nm chips

The Complementary Field-Effect Transistor (CFET: COMPLEMENTARY FET) device architecture is expected to replace the Gate-All-Around (GAA) nanosheet transistor in the logic technology roadmap. In a CFET device, n-type and p-type MOS transistors are stacked together, eliminating for the first time the limitation of the n-p spacing in the standard cell height. Therefore, if combined with advanced transistor contact and power supply technologies, the CFET device architecture is expected to significantly reduce the size of logic standard cells.

Among all possible integration processes, the monolithic CFET (mCFET: monolithic CFET) is considered to cause the least interference and can introduce CFET into devices that meet the actual industrial dimensions at the fastest speed. With monolithic integration, the vertical device structure with shared top and bottom gates can be patterned and processed in a series of process steps.

The vertically stacked layers bring some challenges, and a dedicated CFET module is required to achieve vertical isolation of the critical parts of the stacked cross-section. For example, the Middle Dielectric Isolation (MDI) module can provide isolation between the top and bottom gates. This allows different threshold voltages to be set for the top and bottom devices.

In recent years, significant progress has been made in demonstrating the key building blocks of the 300mm mCFET integration process. At the 2024 VLSI conference, researchers at imec reported an mCFET device with an MDI module that is compatible with the inner spacer - a structure unique to nanosheets that can isolate the gate from the source/drain (S/D). At IEDM 2024, imec experimentally demonstrated a functional mCFET with its backside directly in contact with the source/drain (S/D) of the bottom pMOS device.

Imec expects to introduce the mCFET device architecture at the A7 node (0.7nm) of the logic technology roadmap, at which time mCFET will replace the outer wall forksheet (Figure 1). The latter aims to extend the nanosheet-based logic roadmap to the A10 node in the hope that mCFET can achieve mass production by then.

Scalability of mCFET to More Nodes, a Concern in the Industry

At the circuit level, imec proposes that the double-row CFET architecture is the optimal way to integrate mCFET into A7 standard cells. The double-row CFET standard cell contains two rows of stacked devices, sharing a vertical signal via in the middle, and a "VSS" power wall is provided at the cell boundary. At IEDM 2024, imec demonstrated through a Design-Technology Co-Optimization (DTCO) study how this double-row CFET architecture can achieve the best balance between manufacturing capability and area efficiency at the A7 technology node (Figure 2).

However, the industry has been reluctant to switch to new device architectures because it requires huge tool investments and additional risks. For a successful transition, it is crucial that the new architecture can be used across different nodes.

Therefore, imec researchers continue to conduct DTCO studies to explore the scalability of double-row mCFET at subsequent technology nodes.

To evaluate the power-performance-area (PPA) metrics at the circuit level, the researchers simulated the operation of a 15-stage ring oscillator (i.e., an RO containing 15 mCFET-based inverters). The RO was implemented with increasingly smaller standard cell layouts, complying with the specifications of the A7, A5, and A3 nodes.

To support scalability, the performance per unit of the RO at each node must be maintained within a limited power density budget. The key metric for performance evaluation is the frequency of the RO, expressed as the ratio of the effective drive current to the effective capacitance.

Key Performance Enhancement Measures

As the standard cell size decreases, the thin layer width of a single CFET channel also decreases, thereby reducing the effective drive current and increasing the parasitic capacitance. Therefore, performance enhancement measures are needed to balance these parameters, maintain consistent performance across different nodes, and limit the increase in power density. The M0 power rail can provide additional advantages.

Expanding to the A5 node requires the introduction of the outer wall forksheet device architecture (Figure 3).

Previously, the forksheet structure was considered an extension of the nanosheet device, but its structure is fully compatible with the CFET design. The outer wall and last wall design method of the forksheet structure is attractive because it can enhance the channel stress, thereby increasing the drive current of the CFET device. The shared n-n or p-p walls of the forksheet structure result in a smaller gate extension range, thereby reducing the gate parasitic capacitance. Using the Ω-shaped gate can more effectively wrap the channel, resulting in more advantages.

In addition to the Ω-shaped gate outer wall forksheet and the M0 power rail (Figure 4), the A3 node requires an additional performance enhancer. By introducing a hybrid channel orientation, the effective drive current can be further increased. Adjusting the channel orientation affects the carrier mobility, and the optimal orientation differs for n-type and p-type devices. It should be noted that the optimal choice also depends on whether strain (and the magnitude of the strain) is introduced into the channel. The imec team evaluated various channel orientations and found that the optimal combination can increase the drive current by up to 20%. The resulting increase in power density can be compensated for by balancing the channel width.

Embedded MDI Module

At IEDM 2025, imec experimentally demonstrated a key module: the embedded MDI module, which allows the integration of channels of top nMOS devices and bottom pMOS devices in different directions in the mCFET process flow.

The manufacturing process of eMDI starts with carrier and donor wafers, on which Si and sacrificial SiGe layer stacks unique to CFET are epitaxially grown respectively to form the bottom and top channels. Then, these epitaxial stacks are recombined using wafer fusion bonding technology. The SiCN bonding medium becomes the embedded MDI single-layer film in the mCFET device structure, used to isolate the bottom and top parts. After these steps, the mCFET is fabricated using the traditional mCFET process flow, including nanosheet patterning, Si fin exposure, gate and inner spacer formation, bottom and top source/drain epitaxial growth, and metal gate replacement (Figure 5).

Imec successfully integrated the eMDI module into the complete mCFET process flow and demonstrated functional top devices with different channel orientations: (100) silicon top nFET, (100) and (110) silicon top pFET. These top devices were fabricated using the front-side connection method (Figure 6).

Subsequently, the integration process was further extended to achieve direct backside contact with the mCFET bottom device. The imec CFET team demonstrated a functional mCFET device with an integrated eMDI module, a front-side connected (100) Si top nFET, and a directly backside contacted (110) Si pFET (Figure 7).

Advantages of eMDI

Compared with the earlier version of the MDI module (which imec calls the alternative MDI or rMDI), the eMDI module has several advantages. In rMDI, the active Si/SiGe epitaxial stack is converted into a high Si/SiGe1/SiGe2 multi-layer stack. In the subsequent process flow, the sacrificial layer SiGe1 is replaced by the gate work function metal, while the Ge-rich SiGe2 layer is converted into the MDI dielectric layer.

The main difference between the two methods lies in the initial substrate engineering (Figure 8). In the eMDI scheme, the mCFET process starts with an advanced bonded substrate with a pre-embedded MDI module. Before the first bonding, separate wafers are used to grow the n and pMOS active epitaxial layers, which allows the integration of heterogeneous channels, thereby optimizing the performance of the n and pMOS devices. These channels can be of different orientations (as shown in this study), or channels with different strains, or even n and p channels using different materials.

Other advantages include reduced process complexity and simplified epitaxial growth steps: eMDI avoids the deposition of a complex Si/SiGe1/SiGe2 multi-layer stack structure and does not require the replacement of the dummy SiGe2 layer with a dielectric layer. In addition, by growing the epitaxial stacks on two independent wafers, more Si channels can be added before layer relaxation during the epitaxial growth process, thereby increasing the design flexibility. This new MDI module can be integrated into any mCFET baseline with only minor modifications to the mCFET process.

Different Channel Materials, Embedded Bottom Dielectric Isolation Module

Imec is currently optimizing the key modules for different channel directions in the eMDI-based mCFET process flow. Future work will extend this scheme to integrate different channel materials, such as Ge for pMOS and Si for nMOS.

In addition, the imec CFET team plans to adopt a similar "embedded" approach to integrate the bottom dielectric isolation layer (BDI), a process module used to isolate the source/drain epitaxial layer from the substrate. Compared with the currently used alternative BDI (rBDI) (Figure 9), the eBDI method based on wafer bonding and layer transfer is expected to simplify the integration of backside connections. In addition, the eBDI method also provides more freedom in the selection of BDI materials. One option is to use a high thermal conductivity material, which may alleviate concerns about the thermal reliability of mCFET.

Imec determined through a DTCO study the performance enhancement measures required to support the aggressive area scaling of the mCFET device architecture across multiple technology nodes. While minimizing the parasitic gate capacitance is crucial for the A7 node, the A5 and A3 nodes will introduce the outer wall fork structure with an Ω-shaped gate and the M0 power rail.

For the A3 node, the introduction of heterogeneous channels optimized for p-type and n-type MOS respectively is crucial for maintaining performance and power density at the final scaled standard cell size. The eMDI module is the key enabling technology for the integration of heterogeneous channels in the mCFET process. This has been experimentally verified on mCFET devices with top nMOS and pMOS devices of different channel directions.

This article is from the WeChat official account "Semiconductor Industry Observation" (ID: icbank), author: imec, published by 36Kr with authorization.