The real bottleneck of TSMC

By the end of 2025, TSMC had just completed the architectural innovation of 2-nanometer gate-all-around (GAA) transistors - the most significant change in transistor structure since the advent of FinFET in 2011. We extensively reported on this milestone event, and it was well-deserved. The production equipment intensity per wafer will increase by 30% to 50%, which will drive a multi-year capital expenditure cycle. SEMI predicts that this cycle will reach $156 billion by 2027.

Related reports indicate that TSMC stated that the 2-nanometer technology began mass production as scheduled in the fourth quarter of 2025. The N2 technology uses the first-generation nanosheet transistor technology, providing performance and power consumption improvements across the entire process node. It also develops low-resistance reset wiring layers and ultra-high-performance metal interlayer capacitors to continuously enhance the performance of the 2-nanometer process technology.

TSMC pointed out that the N2 technology will become the most advanced semiconductor technology in the industry in terms of density and energy efficiency. The N2 technology uses a leading nanosheet transistor structure, which will provide performance and power consumption improvements across the entire process node to meet the increasing demand for energy-efficient computing. N2 and its derivative technologies will further expand TSMC's technological leadership due to our continuously strengthened strategy.

Compared with the 3-nanometer N3E process, TSMC's 2-nanometer technology increases the speed by 10% to 15% at the same power consumption; at the same speed, it reduces the power consumption by 25% to 30%, and at the same time, the chip density increases by more than 15%. TSMC will also launch the N2P process technology as an extension of the 2-nanometer family, with mass production planned for the second half of 2026, supporting smartphone and high-performance computing applications.

TSMC's 2-nanometer production has started simultaneously at the Kaohsiung and Hsinchu factories, and the Kaohsiung factory is the top priority for 2-nanometer production. TSMC plans to build five 2-nanometer wafer fabs in Kaohsiung, with a total investment of more than NT$1.5 trillion. The P1 factory began mass production at the end of 2025, and the P2 factory is expected to start mass production in the second quarter of 2026, creating 7,000 high-tech job opportunities and driving the industrial transformation and upgrading of Kaohsiung.

The report also pointed out that benefiting from the explosive demand for AI, the 2-nanometer process will shine this year. The semiconductor industry has newly reported that the maximum monthly production capacity of the 2-nanometer process this year will reach up to 140,000 wafers, more than the market's estimated 100,000 wafers. The mass production of the new process has reached a huge volume in just one year, approaching the 160,000 wafers that the 3-nanometer process will increase to this year, indicating strong demand. The 3-nanometer process has been in mass production for more than three years, and it is currently in short supply.

However, most reports have overlooked one point: the real bottleneck is no longer transistor density, but advanced packaging technology.

NVIDIA occupies more than 70% of TSMC's CoWoS-L chip production capacity. The ultra-large-scale data center giants under Broadcom - Google, Apple, Meta, Anthropic, OpenAI, and ByteDance - compete for the remaining capacity. Even if you have the world's most advanced 2nm computing chips, if they cannot be packaged with HBM memory on the CoWoS interposer, they are just expensive inventory chips.

The GAA transformation and the CoWoS competition are two sides of the same coin. Understanding both is crucial for positioning in this cycle.

Let's delve deeper into this.

The GAA Transformation is Crucial

For anyone who has studied device physics, the scaling problem of FinFET was predictable. FinFET achieves three-gate control by wrapping the gate around three sides of a vertical silicon fin. This method works extremely well at the 7nm and 5nm processes. However, when the gate length is less than 5nm, the calculation results will have catastrophic deviations.

The culprit is drain-induced barrier lowering (DIBL). As the channel size shrinks, the electric field of the drain will penetrate deeper into the channel region, thereby lowering the barrier that prevents current from flowing in the "off" state. Below 5nm, DIBL exceeds 100mV/V - which means that the transistor will leak like a sieve when it should be in the off state. The subthreshold swing also drops from the ideal 60mV/decade to 70 - 90mV/decade.

I remember that the photonics field also encountered a similar scaling bottleneck - at a certain stage, what you face is no longer an engineering problem, but a thermodynamic problem. At Deco Lighting, we finally realized that reaching the physical limit means that we need to rethink the architecture, not just optimize the existing methods.

The GAA nanosheet solves this problem by wrapping the gate around all four sides of horizontally stacked silicon ribbons. TCAD simulations show that compared with a FinFET of the same size, DIBL is reduced by 65 - 83%. This is not a gradual improvement, but a leap in electrostatic control.

Cross-sectional comparison between FinFET and GAA nanosheets

TSMC's N2 solution uses 3 - 4 layers of stacked silicon nanosheets, with each layer about 5nm thick, 10 - 50nm wide, and a layer spacing of 7 - 15nm. Compared with the three-gate structure, the "natural length" of GAA (the natural length that determines electrostatic integrity) is approximately 30% shorter, which is why this architecture can continue to be miniaturized.

From the perspective of design flexibility, what excites me the most is TSMC's "NanoFlex" technology. The variable-width nanosheets on the same chip break through the limitation of quantized width in FinFET design. On the same chip, narrow nanosheets can be used to achieve low-power cores, or wide nanosheets can be used to achieve high-performance cores. This is true architectural freedom.

The roadmap after nanosheets is clear: Forksheet (expected around 2028) introduces a dielectric wall between n/p devices to achieve a smaller pitch, and then CFET (expected around 2032) vertically stacks nMOS directly on pMOS.

The GAA transformation introduces 4 - 5 brand-new process modules, extending the manufacturing process by approximately 20%. And each of these steps requires dedicated equipment.

Silicon/silicon-germanium superlattice epitaxy: Build alternating sacrificial silicon-germanium layers and silicon channel layers and achieve nanometer-level thickness control. This is the area where Applied Materials excels with its Centura Prime Epi platform.

Inner spacer formation: This is the most complex new module. First, form SiGe layer grooves through lateral isotropic etching, then deposit a dielectric layer using conformal LPCVD, and finally perform precise etch-back to form a 9 - 10nm inner spacer. The crescent-shaped spacer profile may cause TDDB reliability failures.

Nanosheet release etching: Selectively removing SiGe while retaining the silicon channel requires a selectivity greater than 100:1. According to industry analysts, Lam occupies approximately 80% of the market share in the selective etching field below 5nm. Their Selis and Prevos platforms are almost irreplaceable.

Replacement metal gate: Depositing high-dielectric-constant and high-work-function metals into the space between the suspended sheets pushes atomic layer deposition (ALD) technology to the limit. Applied Materials' IMS platform achieves an equivalent oxide thickness advantage of approximately 1.5 angstroms compared to competitors' products.

Explosive growth in metrology technology: KLA reported that compared with FinFET, GAA drives a 30% increase in high-end thin-film metrology layers and a 50% increase in critical inspection layers.

Applied Materials directly quantified this: The equipment revenue for every 100,000 wafers/month of production, including GAA and backside power delivery, increases from approximately $6 billion to $7 billion. This is a structural demand increase independent of production volume.

CoWoS is the Real Constraint

Most semiconductor industry reports have overlooked a key piece of information: advanced packaging capabilities (rather than transistor density) have become the key factor restricting the leadership in AI chips.

You can have the world's most advanced 2nm computing chips, but if they cannot be packaged with HBM memory in the CoWoS interposer, they are just expensive silicon wafers in inventory.

Let me explain why advanced packaging has become a bottleneck - the "basic" part that most products overlook.

Photomask area limitation problem: A single extreme ultraviolet lithography exposure can only pattern an area of approximately 858 square millimeters ("photomask area limitation"). NVIDIA's GB100 chip area has reached 814 square millimeters - basically reaching the limit. To build a larger system, multiple chips must be connected together. This is where packaging technology comes in.

Interposer challenge: CoWoS places multiple chips on a silicon or organic interposer, enabling ultra-high-density wiring between chips. The original CoWoS-S used a single-piece silicon interposer, but silicon becomes fragile and prone to deformation after exceeding about 3.3 times the photomask size (about 2700 square millimeters). Therefore, TSMC developed CoWoS-L.

The nightmare of mismatched coefficients of thermal expansion: Different materials have different coefficients of thermal expansion. When a GPU chip (silicon), an LSI bridge chip (silicon), an organic interposer (polymer), and a substrate (laminate) are bonded together and the system operates at a power of 1400W, the mismatched coefficients of thermal expansion can cause warping, cracking, and connection failures. This is why the release of the Blackwell processor was postponed to the third to fourth quarters of 2024.

HBM integration complexity: Each HBM3e stack contains 8 - 12 DRAM chips, which are connected through thousands of through-silicon vias (TSVs) and bonded with microbumps at a pitch of 20 - 30 microns. The HBM4, expected to be launched in 2026, will reduce the microbump pitch to 10 microns and use a 2048-bit interface. Yield calculation is extremely demanding - if there is a single bad connection among thousands of connections, the entire package will be scrapped.

TSMC CEO C.C. Wei confirmed: "The supply is still very tight, and this situation may last until 2025. I hope the situation can improve in 2026."

Although the production capacity doubled in both 2024 and 2025, the demand still exceeds the supply.

The price says it all: The average selling price of advanced packaging increases by 10 - 20% annually, while the average selling price of logic wafers only increases by 5%. TSMC's packaging business currently accounts for approximately 7 - 9% of its revenue, with a profit margin close to the company's average (gross profit margin of approximately 53%).

Morgan Stanley's detailed analysis reveals the asset allocation hierarchy:

NVIDIA is expected to have more than 70% of the share in CoWoS-L (the variant required for the Blackwell dual-chip design), which creates a structural advantage but also brings concentration risk if TSMC decides to diversify.

However, according to the latest reports from Taiwan media, due to the rising demand for GPU/ASIC driven by cloud AI, the supply shortage of CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging has intensified. To meet the strong demand for AI chips, TSMC is accelerating the expansion of CoWoS production capacity.

1. Significant upward revision of production capacity: Domestic institutional investors have revised up their forecast for TSMC's CoWoS production capacity at the end of 2026 by 14%, reaching 125Kwpm (thousands of wafers per month), and it is expected to further increase to 170Kwpm by the end of 2027.

2. Diversification and technological layout: TSMC's advanced packaging technology is developing towards diversification. In addition to the strong demand for CoWoS, the SoIC (System-on-Integrated-Chips) technology has been applied in products such as AMD's MI300, and NVIDIA and Broadcom are also expected to adopt it after 2027. In addition, Apple's A20 chip is expected to adopt WMCM (Wafer-level Multi-Chip Module) for the iPhone 18/foldable phone.

3. New technology R & D: TSMC is developing the CoPoS (Chip-on-Package-on-Substrate) technology, which is expected to be adopted in AI/HPC-related chips after 2027, aiming to improve packaging area utilization, production efficiency, and reduce costs.

It is reported that TSMC's advanced packaging factories are widely distributed, including Longtan (AP3), Taichung (AP5), Zhunan (AP6), Chiayi (AP7), Tainan (AP8), etc. Among them, the expansion of AP