300mm Gallium Nitride, Global Premiere
At IEDM 2025, Intel first demonstrated a GaN Chiplet technology based on a 300mm silicon-based gallium nitride process. This GaN Chiplet technology has the following features:
- The thinnest GaN Chiplet in the industry, with an underlying silicon substrate thickness of only 19µm. It is taken from a fully processed, thinned, and single-crystallized 300mm silicon-based gallium nitride wafer and demonstrates excellent transistor performance and figure of merit.
- The industry's first fully functional integrated on-chip CMOS digital circuit library that uses monolithic integration of GaN N-MOSHEMT and silicon PMOS processes, covering inverters, logic gates, multiplexers, flip-flops, and ring oscillators, etc.
- The test results of TDDB, pBTI, HTRB, and HCI are satisfactory, indicating that this 300mm GaN MOSHEMT technology can meet the required reliability indicators.
Intel believes that the technological elements demonstrated in this work indicate that 300mm GaN-on-silicon technology is an attractive and powerful Chiplet technology suitable for high-performance, high-density, high-efficiency power, and high-speed/radio frequency electronic products.
Introduction
As computing solutions expand towards higher power for applications in graphics and server platforms, and as emerging 5G/6G communications continuously increase data rates, semiconductor technologies such as gallium nitride (GaN) and advanced 3D packaging are playing an increasingly important role in providing higher performance, higher efficiency, higher integration, and higher density beyond current silicon and III-V technologies.
Previously, experts proposed 300mm GaN-on-silicon technology. Due to its excellent figure of merit (FoM) and the ability to integrate low-voltage to 48V GaN with silicon CMOS, it is becoming an attractive technology in the fields of high-density, high-performance power, and high-speed/radio frequency electronic devices. Figure 1 shows the potential development direction of GaN point-of-load power solutions: from discrete motherboard voltage regulators (MBVR) to Chiplet integration using GaN power chips to meet the requirements for higher power density, higher efficiency (e.g., reducing I²R wiring losses), and closer integration.
This article demonstrates the technological elements required to implement GaN Chiplet technology based on a 300mm silicon-based GaN process. Figure 2 shows an example of GaN Chiplet integration.
First, it is worth noting that the space available for accommodating Chiplets in this composite structure is very limited (in all xyz directions). Therefore, GaN transistor technology needs to have high density and high performance, capable of providing a high current density close to or exceeding 10 A/mm². Previously, we demonstrated that 300mm silicon-based GaN MOSHEMT technology can achieve power chips with a current density close to ~10 A/mm². In addition, GaN Chiplets need to be ultra-thin (<<50 µm) to enable short (low aspect ratio), low-resistance through-silicon vias (TSVs), thereby reducing resistance losses and achieving acceptable heat dissipation.
In this work, we demonstrate the industry's first GaN Chiplet with a silicon substrate thickness of only 19 µm, taken from a fully processed, thinned, and single-crystallized 300 mm GaN on-silicon wafer.
Second, GaN Chiplets must be as complete as possible, with various required functions, such as CMOS controllers, low-leakage CMOS drivers, bias circuits (e.g., PMOS current mirrors), and telemetry circuits. Integrating functions such as CMOS drivers (e.g., DrGaN) and dead-time controllers is crucial for achieving optimal efficiency and fast switching to reduce the size of passive components. There is no space in this complex structure for, for example, CMOS companion chips. Wiring between chips just to access a small number of CMOS components is inefficient.
Therefore, for GaN Chiplet technology, it is crucial to integrate and implement key CMOS elements on the same GaN chip.
To this end, we first demonstrate a fully functional, fully integrated on-chip CMOS digital circuit library, covering inverters, logic gates, multiplexers, flip-flops, and ring oscillators, etc. All circuits are implemented using a monolithic integration of GaN N-MOSHEMT and Si PMOS processes, which are realized through layer transfer technology and designed using a unified process design kit (PDK).
Third, GaN MOSHEMT transistor technology must meet basic reliability requirements. In this work, we demonstrate good results in terms of time-dependent dielectric breakdown (TDDB), positive bias temperature instability (pBTI), high-temperature reverse bias (HTRB), and hot carrier injection (HCI), indicating that 300mm GaN MOSHEMT technology can meet these reliability indicators.
Fabrication of Ultra-Thin GaN Chiplets from High-Performance 300 mm Silicon-Based Gallium Nitride Wafers
Figure 3 shows a photo of a thinned and singulated 300 mm GaN-on-silicon wafer, including (b) the wafer edge and (c) the area where a Chiplet (die) was successfully removed from the wafer. The wafer was thinned and singulated using the SDBG (stealth dicing before grinding) process.
Figures 4(a-c) show SEM micrographs of a GaN Chiplet extracted from the 300 mm GaN-on-silicon wafer shown in Figure 3, showing an underlying silicon substrate with a thickness of only 19 µm. Cross-sectional SEM micrographs show the fully processed back-end interconnect stack and front-end GaN devices. It should be emphasized that this is the thinnest fully processed 300 mm GaN wafer in the industry. Figure 4(d) shows a prototype where the top GaN Chiplet is flipped and connected to the bottom wafer.
Figure 5 shows the ID-VG characteristics of GaN MOSHEMT (LG = 30 nm, different gate-drain spacings) transistors measured from the GaN Chiplet in Figure 4. The GaN transistor with LG = 30 nm exhibits excellent on-resistance (RON) and low drain and gate leakage currents below 3 pA/µm.
Figure 6 shows the ID-VD characteristics of a GaN MOSHEMT (LG = 30 nm, LGD = 1000 nm, LGFP = 900 nm) measured from the GaN Chiplet in Figure 4. During the BVDS measurement in Figure 6(b), after maintaining a VDS of 78 V (@ 1 µA/µm), the transistor exhibits stable ID-VD characteristics (change less than 2%).
Figure 7 shows the Ron-BVDS and BVDS-LGD characteristics of LG = 30nm GaN MOSHEMTs with different LGD and LGFP values, measured from the GaN Chiplet in Figure 4.
Figure 8 shows that the optimal power FoM = Ron-QGG ~1 mΩ-nC is achieved by a GaN MOSHEMT with LG = 30nm and LGD = 200 - 250nm, measured from the GaN Chiplet in Figure 4. Previously, our 300mm silicon-based GaN MOSHEMT technology using GaN MOSHEMTs with a relatively long channel length (LG = 250nm) achieved a current density of approximately 10 A/mm². This article shows that by reducing the transistor geometry and spacing, a short channel length (LG) of up to 30nm can be achieved, making it possible to achieve a current density much greater than 10 A/mm².
Figure 9 shows the radio frequency performance of GaN MOSHEMT transistors. For the shortest LG of 30 nm, high fT/fMAX values of 212/304 GHz are achieved; within the range of LG up to 130 nm, the peak fMAX is greater than 200 GHz. The radio frequency data measured here (based on the GaN Chiplet in Figure 4) indicates that this device has good application prospects in radio frequency and high-speed applications (e.g., photonics). This GaN Chiplet technology has potential application value in these applications.
Integration of CMOS Digital Circuits and GaN MOSHEMTs on 300mm Silicon-Based GaN
Figure 10 is a transmission electron microscope (TEM) image of GaN N-MOSHEMT transistors and Si PMOS monolithically integrated on a 300mm silicon-based GaN wafer.
Figure 11 shows the ID-VG characteristic curves of a monolithically integrated Si PMOS transistor (LG = 180 nm, RON = 2411 Ω-µm, ION = 0.35 mA/µm) and a GaN MOSHEMT transistor (LG = 180 nm, RON = 413 Ω-µm, ION = 1.03 mA/µm).
Figure 12 shows an inverter implemented using monolithic integration of GaN N-MOSHEMT and Si PMOS, showing the measured inverter Vout-Vin response and input/output waveforms.
Figure 13 shows a NAND gate and its measured output waveform and (p, q) input waveforms.
Figure 14 shows a multiplexer (MUX), showing the measured output waveforms of the (p, q) and Select input signals.
Figure 15 shows the layout of a ring oscillator implemented using the same monolithic process. This oscillator contains 7,213 stages of inverters and a 214-frequency divider (composed of a chain of D flip-flops). On a 300 mm GaN-on-Si wafer, the measured delay per stage of the inverter is 33 ps ± 2 ps (1σ). This is the first time that a fully functional on-chip integrated digital circuit library has been demonstrated using a 300 mm monolithic integration of GaN N-MOSHEMT and Si PMOS processes.
