Top 10 predictions for the semiconductor industry: How far have we come?

As 2025 draws to a close, it's time to assess the "Top Ten Semiconductor Technology Trend Predictions" that dominated headlines at the beginning of the year. Core areas such as 2nm, HBM4, advanced packaging, AI processors, intelligent driving chips, and quantum processors have remained the focus of the industry. So, how much progress has been made on these predictions over the past year? Today, let's follow the timeline to dissect the real advancements in these ten key directions.

01 How Much of the Top Ten Semiconductor Predictions Have Been Fulfilled?

2nm: From "Who Will Mass-Produce First" to "Who Can Deliver Stably"

At the beginning of the year, it was widely predicted that 2025 would be the "year of mass production" for the 2nm process. Now, it seems that this goal has been largely achieved, but with a "phased" label.

In previous predictions, TSMC, Samsung, and Intel all planned to launch 2nm or equivalent processes (such as Intel 18A) in 2025. As of now, TSMC started accepting orders for its 2nm process in April this year and plans to start mass production later in the fourth quarter. Its customers include leading chip manufacturers such as Apple, NVIDIA, AMD, Qualcomm, and MediaTek.

TSMC Chairman Mark Liu said that the demand for 2nm chips has exceeded that of the 3nm generation. To meet the growing order demand, TSMC is planning to expand its production capacity. As of now, TSMC has planned a total of seven 2nm wafer fabs, two in the Hsinchu Science Park and five in the Kaohsiung Nanzih Export Processing Zone. If the three new factories are successfully established, the total number of its 2nm dedicated wafer fabs will increase to ten.

Samsung Electronics has officially started mass-producing its first 2nm process mobile application processor, the Exynos 2600, and the current yield rate has stabilized at 50%-60%. However, this news has not had a significant impact on the market. The core reason may be the uncertainty of the 2nm process yield rate, combined with the technical implementation and cost control issues that its 3nm process exposed during the mass production stage, which has led the industry to adopt a wait-and-see attitude towards the large-scale supply capacity and market competitiveness of this flagship chip.

Intel's 18A process has entered large-scale mass production at the Fab 52 factory in Arizona. This process uses gate-all-around transistor technology and backside power delivery technology, achieving dual improvements in energy efficiency and density.

It should be noted that "mass production" does not equal "large-scale supply." Currently, the production capacity of 2nm chips is extremely limited, mainly serving high-premium customers, and it will still take at least six months to a year before they are widely available in consumer products. The real surge in production will not come until 2026.

HBM4: SK Hynix Takes the Lead Again

If 2024 was the year of the HBM3E explosion, then 2025 is undoubtedly the starting year of HBM4.

In September this year, six months after delivering 12-layer HBM4 samples to major customers such as NVIDIA, SK Hynix completed the development of its HBM4 memory chips and entered the mass production stage. Its HBM4 products will start shipping in the fourth quarter of this year and are planned to be sold on a larger scale next year.

The price negotiation between Samsung Electronics and NVIDIA for the supply of HBM4 is in its final stage. Samsung Electronics is avoiding the mistakes that led to its loss of the dominant position in the DRAM field and is using the large-scale production of HBM4 based on the more advanced 1c DRAM to ensure its competitive advantage over SK Hynix's HBM4 based on 1b DRAM. However, Samsung's HBM4 products are still in the final testing stage, and industry insiders predict that the large-scale shipment time may be in 2026.

Advanced Packaging: Blooming in Multiple Areas

Advanced packaging has become the core path to continue Moore's Law. In 2025, it is not only a year of significant CoWoS production capacity release but also a crucial node for the layout of the next-generation co-packaged optics (CoPoS) technology.

TSMC has launched the Chunghwa Picture Tubes Nanke Factory (AP8) as the main production base for CoWoS-L and completed full-capacity operation in the second half of the year. Factories in Zhunan, Longtan, etc., are also adjusting their production capacity to meet the future demand growth for technologies such as CoWoS-L and InFO-M.

It is worth noting that while TSMC is continuously expanding its CoWoS production capacity, it is also accelerating the R&D and factory construction of CoPoS technology. The company released the first batch of supplier lists and equipment specifications ahead of schedule in the third quarter of 2025. TSMC plans to build the first CoPoS pilot production line at VisEra in 2026, and mass production will be carried out at its Chiayi AP7 factory.

Recently, Morgan Stanley analysts released a report stating that TSMC's monthly CoWoS production capacity will reach at least 120,000 to 130,000 wafers by the end of 2026, higher than the previously estimated 100,000 wafers. This significant upward adjustment is based on the bank's latest industry survey.

Meanwhile, domestic packaging and testing manufacturers are also accelerating their catch-up. In the first half of 2025, the dedicated automotive-grade chip packaging and testing base of Changjiang Electronics Technology was completed, and it will be put into production in the second half of the year. The first phase of the project of Tongfu AMD (Suzhou) Microelectronics Co., Ltd. achieved mass production in January 2025, engaging in high-end advanced packaging and testing of FCBGA. The Jiangsu Pangu Semiconductor board-level packaging and testing project of Huatian Technology is committed to promoting the large-scale mass production of board-level fan-out packaging technology and also partially started production this year.

NVIDIA Blackwell Ultra GB300: A Blockbuster Arrival

In March this year, at the GTC 2025 conference, NVIDIA officially launched its new Blackwell Ultra GB300 chip and entered the large-scale mass production stage in the third quarter. The new B300 GPU will provide higher computing throughput than the B200, and the 50% more on-chip memory will be able to support AI models with larger parameter quantities, and the corresponding computing power will surely be helpful. In addition, NVIDIA also previewed its next-generation chip, "Rubin," which is expected to be launched in the second half of 2026. The performance of the Rubin chip will be even better, with its FP4 inference performance reaching 50 petaflops, more than twice that of the current Blackwell chip.

In June this year, at the ADVANCING AI 2025 summit, AMD announced its new CDNA 4 GPU architecture and launched the AMD Instinct MI350 series of GPUs and the new ROCm 7. As the first AI accelerator card using the CNDA 4 architecture, the Instinct MI350 series of GPUs includes the Instinct MI350X with a peak power consumption of 1000W for air-cooled systems and the more powerful Instinct MI355X with a peak power consumption of 1400W for liquid-cooled systems. In addition to the new Instinct MI350 series of GPUs, AMD also pre-disclosed the MI400 series of GPUs to be launched in 2026, which will bring AI high-performance computing GPU products into a new era.

Intel announced that it will globally debut the third-generation Core Ultra "Panther Lake" processor at the CES 2026 exhibition.

In addition to the successive launches of new AI chips, the most significant change in 2025 is the diversification of the AI processor landscape. In this year, the ASIC camp represented by Google also made breakthrough progress.

Actual test data shows that when processing specific AI models, the computing speed of the TPU can reach one and a half to two times that of the same-generation NVIDIA GPU, and the energy efficiency is improved by about 30%. This performance advantage stems from Google's "software-hardware integration" design concept - the TPU is optimized for the TensorFlow framework and is deeply customized from the chip architecture to the compiler. However, NVIDIA's confidence lies in the versatility advantage of its GPU. The A100 chip not only supports all mainstream AI frameworks but also can handle multiple tasks such as graphics rendering and scientific computing.

Domestic Automotive-Grade Chips: Accelerating into Vehicles

2025 is also regarded by many automotive-grade chip manufacturers as the final stage of high-level intelligent driving and the window period for mass production and installation in vehicles.

On November 22, Horizon Robotics disclosed that its high-level intelligent driving solution, HSD (Horizon SuperDrive), has won orders from ten domestic and foreign automobile brands for more than 20 models. It is equipped with the Journey 6P chip with a maximum computing power of 560 TOPS and can deploy large models such as end-to-end, VLA, and VLM. In addition, the cumulative shipments of its Journey series of chips have exceeded 10 million units, making it the first domestic enterprise to achieve shipments of tens of millions of intelligent driving chips.

The Journey 6P uses a multi-core heterogeneous architecture, and its computing power resources support the rapid implementation of high-level assisted driving. Horizon Robotics said that the HSD solution covers high-speed, urban, and parking scenarios and has launched mass production cooperation with international leading automobile manufacturers. It is expected to be installed in vehicles successively starting from 2026.

The Wudang C1200 family of intelligent vehicle cross-domain computing chip platforms of Black Sesame Technologies was launched in April 2023. It is the industry's first cross-domain computing SoC platform designed for intelligent vehicles and can meet the highest reliability requirements of automotive safety levels. Among them, the C1236 chip is for high-level intelligent driving, and a single chip supports the integration of NOA driving and parking; the C1296 chip supports cross-domain fusion on a single chip. Based on the C1200 family, Black Sesame Technologies has reached cooperation with many customers, including FAW Hongqi, Wind River, Joonlink, and Zebra Intelligence, among other vehicle manufacturers and ecological partners.

In March this year, Xinqing Technology officially launched its full-scenario high-level autonomous driving 7nm chip, "Xingchen No. 1," and the corresponding full series of solutions for intelligent cockpits and intelligent driving. The corresponding chips will be widely used in vehicles next year. This chip uses a 7nm automotive-grade process, meets the AEC-Q100 standard, and introduces a multi-core heterogeneous architecture to make the intelligent driving computing power more powerful. The CPU computing power reaches 250 KDMIPS, and the NPU computing power is as high as 512 TOPS. Through multi-chip collaboration, a maximum computing power of 2048 TOPS can be achieved.

Quantum Processors: Still Laying the Foundation

At the beginning of the year, there was a view that "in 2025, quantum processors will enter the stage of practical exploration." Looking back now, this judgment is basically valid, but it is still too early to talk about "practicality."

Recently, technology giant IBM launched two experimental quantum chips, Loon and Nighthawk. However, according to the latest revised roadmap released recently, IBM has planned its path from 2025 to 2033 and beyond. The roadmap shows that the Kookaburra, which was mentioned in the prediction at the beginning of the year, will be launched in 2026. This will be the first quantum processor module that can store information in the qLDPC memory and process information through the additional LPU, expanding the fault-tolerant system beyond a single chip.

In 2027, the Cockatoo will use L-couplers to achieve entanglement between two Kookaburra modules, thus connecting quantum chips together like nodes in a large system and avoiding the construction of an unrealistic large chip. In 2029, IBM will deliver the world's first large-scale fault-tolerant quantum computer, the IBM Quantum Starling.

These achievements are of great significance at the scientific level, proving the feasibility of fault-tolerant quantum computing, but there is still a long way to go before mature applications. Quantum processors are still a "future technology," and the progress made in 2025 is more about "laying the foundation" than "building the building."

Silicon Photonics and CPO: The 1.6T Era Quietly Begins

As the requirements of AI clusters for bandwidth and power consumption approach the limit, silicon photonics integration and co-packaged optics (CPO) have become popular options.

In 2025, Broadcom, Cisco, and Ayar Labs jointly promoted CPO technology, significantly reducing power consumption during the transition from 800G to 1.6T. Meta and Microsoft have tested CPO switches in some AI clusters to verify their reliability.

TSMC has successfully combined co-packaged optics (CPO) technology with advanced semiconductor packaging technology. It is expected to start providing samples from the beginning of 2025. This achievement indicates that TSMC will enter the 1.6T optical transmission era in the same year. According to industry predictions, Broadcom and NVIDIA are expected to be the first users of TSMC's solution.

LightCounting predicts that the global shipment volume of 800G optical modules will exceed 5 million units in 2025, of which the proportion of the LPO solution is expected to exceed 40%, while this figure was less than 500,000 units in 2023. 800G optical modules, especially those using LPO technology, are in a stage of rapid development and are playing an increasingly crucial role in the era of the AI computing power explosion, continuously driving the reshaping and transformation of the data center optical interconnection landscape.

After 800G optical modules, as AI server clusters put forward higher requirements for interconnection rates, NVIDIA has chosen to switch to 1.6T optical modules in its GB300 servers and also provides the option to upgrade to 1.6T optical modules in its GB200 servers. Therefore, 1.6T optical modules have started to take the stage.

Regarding the future development prediction, the 1.6T rate will be reached in the next one to two years. It is expected that by 2029, the optical module rate for AI applications will reach 3.2T, and 3.2T will move towards large-scale application in 2030.

Entering the Core Battlefield of AI Computing

In 2025, RISC-V is no longer just a synonym for "low-power MCUs" but has officially entered the core battlefield of AI computing.

Actually, as early as 2024, the performance of the third-generation "Xiangshan" open-source high-performance RISC-V processor core jointly released by the Institute of Computing Technology of the Chinese Academy of Sciences and the Beijing Open Source Chip Institute had entered the first echelon. In addition, a number of domestic enterprises such as CoreXing Technology, Yiswim, and Jindie Times released IPs, toolchains, software platforms, chips such as AI PC chips, AI MCUs, and multimedia processors, as well as development boards and other products.

Judging from the current implementation progress, RISC-V is simultaneously advancing in three high-value areas - edge AI, intelligent vehicles, and data centers. It is no longer limited to low-power IoT devices but shows the ability to penetrate cross-level scenarios: it can be embedded in a voice wake-up chip, support the decision-making system of an intelligent vehicle, and even become the trusted foundation of a cloud data center.

In the process of promoting the in-depth integration of RISC-V and AI, Yiswim Computing, China Mobile CoreXing, and Jindie Times have all taken relevant actions. In the automotive scenario, Infineon and Mobileye have successively released ADAS solutions. NVIDIA is actively promoting the transplantation of CUDA to the RISC-V architecture, which means that developers can freely choose the data center CPU architecture, which will promote the wide application of RISC-V in the field of high-performance computing at the ecological level.

RISC-V International predicts that by 2031, RISC-V chips will occupy a significant share in six major markets: consumer electronics (39%), computers (33%), automobiles (31%), data centers (28%), industry (27%), and network communication (26%), and the total shipment volume will exceed 20 billion units.