The ultimate technology favored by TSMC

At the just-concluded IEDM 2025, TSMC for the first time confirmed the operation of integrated circuits using the next-generation transistor technology - Complementary Field-Effect Transistor (CFET).

According to the previous official preview of IEDM, TSMC announced two important milestones at this year's conference: the first fully functional 101-stage 3D monolithic Complementary Field-Effect Transistor (CFET) Ring Oscillator (RO) and the world's smallest 6T SRAM bit cell, which offers both high-density and high-current designs.

It is reported that based on the previous nanosheet-based monolithic CFET process architecture, TSMC researchers introduced new integration features, further reducing the gate pitch to below 48nm. They also adopted Nanosheet Cut Isolation (NCI) technology between adjacent FETs and Butt Contact (BCT) interconnection technology within the 6T SRAM bit cell to achieve cross-coupling of inverters. Electrical characteristic analysis compared two ring oscillator layouts, highlighting the impact of the 6T bit cell on performance and robust SRAM device metrics.

These advancements mark a crucial shift in CFET development, moving from device-level optimization to circuit-level integration.

TSMC's New Progress

CFET is a technology that increases transistor density by vertically stacking n-channel FETs and p-channel FETs (the basic components of CMOS devices). Theoretically, compared with the current state-of-the-art transistor technology, the nanosheet FET (NS FET), the transistor density can be nearly doubled.

However, the technical difficulty is approaching its limit. First of all, the manufacturing of nanosheet field-effect transistors (FETs) is already very difficult. For capacitive field-effect transistors (CFETs), nanosheet field-effect transistors are vertically stacked in a monolithic manner (such as TSMC's CFET), so naturally, the manufacturing difficulty will further increase.

To date, the research results of CFETs have been limited to single transistors (strictly speaking, a structure composed of two stacked transistors). At last year's IEDM conference, TSMC announced the prototype design and operation results of a CFET inverter element (an element used to invert logical values).

Dr. Yuh-Jier Mii of TSMC first explored the evolution from FinFET to nanosheet FET and then to the vertically stacked complementary or CFET architecture in his speech at IEDM 2024. He explained that compared with nanosheet devices, the density of CFET devices is increased by 1.5 to 2 times, so it is very likely to continue to drive the expansion of Moore's Law. He also introduced the work TSMC has done to implement CFET technology. At that time, they also demonstrated the industry's first and smallest 48nm pitch CFET inverter.

Yuh-Jier Mii explained that TSMC's demonstration at IEDM 2024 achieved a major milestone in the development of CFET technology, which will help drive the future scale-up of the technology. The latest research results are a continuation of this foundation.

It is reported that TSMC fabricated two integrated circuit prototypes: one is a "ring oscillator", which is the basis of logic circuits; the other is an "SRAM cell", which is the basis of memory circuits. The scale of the ring oscillator is particularly large, containing 800 to 1000 transistors.

The ring oscillator consists of an enabling NAND logic element (a feedback element for the ring oscillator output) and 100 inverter elements, thus forming a 101-stage ring oscillator. The operating voltage range of the ring oscillator prototype is from 0.5V to 0.95V. As the power supply voltage increases, the oscillation frequency increases, and the fluctuation of the oscillation frequency decreases. The specific value of the oscillation frequency was not disclosed.

The SRAM cell uses a standard six-transistor circuit configuration. We fabricated two types of SRAM cell prototypes: one is the HD (High Density) type that prioritizes storage density, and the other is the HC (High Current) type that prioritizes performance (driving current). Both types have been verified to work properly. The area of the HD-type cell is 30% smaller than that of the nanosheet FET cell using almost the same design rules. If CFET technology is used, the area of the HD-type cell is 20% smaller than that of the HC-type. However, the read current of the HC-type cell is 1.7 times that of the HD-type cell.

The SRAM cell circuit has a unique connection method called "cross-coupling", which requires Butt Contacts (BCT) to interconnect the upper and lower FETs.

The operating voltage range of the prototype HD-type SRAM cell is from 0.3V to 1.0V. When the power supply voltage is 0.75V, the Read Static Noise Margin (RSNM) is 135mV, the read current is 17.5μA, and the Write Margin (WM) is 265mV. The parameters of this SRAM cell have not been optimized and there is still room for improvement.

The target time for the practical application of CFET technology in the fields of logic and memory is the 2030s. The currently developed integrated circuits are still in a very early stage, and there is still a long way to go before practical application. It can be said that only the first one or two steps have been taken. We look forward to future development.

According to Yuh-Jier Mii's report at IEDM 2024, significant progress has also been made in transistors using two-dimensional channel materials. TSMC has for the first time demonstrated the electrical performance of single-layer channel transistors in a stacked nanosheet structure similar to the N2 technology. In addition, an inverter using well-matched N-channel and P-channel devices with an operating voltage of 1V has been developed. A summary of this work is shown in the figure below.

Looking to the future, TSMC also plans to continue developing new interconnection technologies to improve interconnection performance. For copper interconnections, a new via scheme is planned to reduce via resistance and coupling capacitance. In addition, a new copper barrier layer is being developed to reduce copper wire resistance.

In addition to copper, a new type of metal material with air gaps is currently being developed, which is expected to further reduce resistance and coupling capacitance. Intercalated graphene is another promising new metal material that is expected to significantly reduce interconnection delay in the future. A summary of relevant research results is shown in the figure below.

Industry Giants Are Keeping Up

In addition to TSMC, Samsung and Intel are also paying attention to CFET.

It is understood that Intel was the first among the three companies to demonstrate CFET, releasing an early version as early as the IEDM exhibition in 2020. At IEDM 2023, Intel announced several improvements to the most basic circuit of CFET - the inverter. A CMOS inverter sends the same input voltage to the gates of two devices in the stack and produces an output that is the inverse of the input logic.

An Intel spokesperson told reporters at the time: "The inverter is integrated on a fin." He said: "After maximum shrinkage, its size will be only 50% of that of a normal CMOS inverter."

The problem is that stuffing all the interconnections required for a dual-transistor stacked circuit into the inverter circuit will offset the area advantage. To keep the circuit compact, Intel tried to reduce the congestion associated with connecting the stacked devices. In current transistors, all connections come from above the device. But Intel introduced a technology called backside power delivery, which allows interconnections to exist both above and below the silicon wafer. Using this technology to connect the bottom transistor from below instead of above significantly simplifies the circuit. The resulting inverter has a Contacted Poly Pitch (CPP) of 60 nanometers (essentially the minimum distance between adjacent transistor gates).

Samsung's process is even smaller than Intel's, demonstrating devices with 48-nanometer and 45-nanometer Contacted Poly Pitch (CPP), while Intel's process is 60 nanometers. However, these results are only for single devices, not complete inverters. Although the performance of the smaller of Samsung's two prototype CFETs declined, the decline was not significant. The company's researchers believe that this problem can be solved by optimizing the manufacturing process.

The key to Samsung's success lies in its ability to electrically isolate the source and drain of the stacked pFET and nFET devices. If the isolation is insufficient, the device that Samsung calls a 3D Stacked FET (3DSFET) will leak electricity. The key step in achieving this isolation is to replace the traditional wet etching process with a new dry etching process. This has increased the yield of qualified devices by 80%.

Like Intel, Samsung also uses the method of contacting the bottom of the device from below the silicon wafer to save space. However, unlike the American company, this South Korean chip manufacturer uses only one nanosheet in each paired device, while Intel uses three. According to its researchers, increasing the number of nanosheets will improve the performance of CFET.

At IEDM 2024, IBM Research and Samsung jointly demonstrated a device called the "Monolithic Stacked Field-Effect Transistor", which uses a stepped channel design where the lower channel is wider than the upper channel, thus reducing the stacking height and alleviating the challenges posed by the high aspect ratio. This research also covers the isolation technology of the channel and source/drain regions, as well as the application of dual work function metals.

CFET Is the Inevitable Path

Some experts believe that before the arrival of the CFET era, the industry will experience three generations of nanosheet architectures and the resulting stagnation in the size reduction of CMOS components (such as SRAM). According to imec (the company that developed the CFET concept around 2016), the stagnation in size reduction will force designers of high-performance computing chips to split CMOS functions such as SRAM and adopt the workaround of splicing old process nodes and chiplets.

imec believes that some traditional technologies, such as analog circuits or I/O, may need to be integrated using different solutions. For example, chipset technology can be used to integrate analog circuits or I/O. At least some logic circuits and SRAM can achieve scalability by using the CFET architecture. This is their expectation.

imec expects that by 2032, the speed of process node shrinkage will slow down, which will force people to rely more on the hybrid use of chips and advanced packaging, as well as those high-performance logic components that are still shrinking.

However, it is very difficult to achieve CMOS device scaling with only nanosheets. Therefore, imec believes that only with CFET can we truly continue to shrink device sizes. Of course, it can also be combined with other technologies (such as chiplets and advanced packaging) to improve chip performance. CFET is paving the way for the continuous scaling of devices. This is exactly the advantage of CFET.

Imec expects that around 2032, the CFET device architecture will surpass the 1-nanometer node.

However, we must also admit that although CFET is expected to resume the pace of process size reduction, there are still several obstacles to overcome before the new architecture can be commercialized. For example, how to power the CFET structure is a difficult problem that needs to be faced first. In addition, because the CFET structure is taller in 3D shape than the nanosheet structure, the increase in the structure aspect ratio also poses challenges to the manufacturing process.

In TSMC's view, the "major challenges" of the CFET architecture may lead to an increase in process complexity and cost.

Therefore, in order to overcome these challenges, manufacturers must carefully select integration solutions that can reduce process complexity and minimize the need for new materials and process capabilities. In addition, it is also crucial to start EDA/process tool development early to prepare for major design changes.

All in all, although it is a good technology, it still needs time.

This article is from the WeChat official account "Semiconductor Industry Observation" (ID: icbank), author: Editorial Department. It is published by 36Kr with permission.