Who will divide up the CoWoS production capacity in 2026?

As transistor miniaturization approaches its physical limits, advanced packaging has become the "second core battleground" determining chip performance.

The emergence of EMIB comes at just the right time.

01

Who Will Divide Up the CoWoS Production Capacity in 2026?

CoWoS (Chip-on-Wafer-on-Substrate) is truly a "hot commodity" in the AI era.

As TSMC's core technology on the path of "More than Moore's Law", the Chip-on-Wafer (CoW) process stacks and bonds multiple chips (such as GPUs, CPUs, and HBMs) onto a silicon interposer wafer. Then, the CoW chips are integrated with the packaging substrate to form a complete CoWoS packaging structure.

This means it allows the integration of GPU computing units using advanced 5nm/3nm processes, HBM chips optimized for storage, and I/O interface chips using mature processes into a single system-level package, finding the optimal balance among performance, power consumption, and cost.

In the AI computing power competition, the high-bandwidth advantage of CoWoS is indispensable. Data shows that the data transmission bandwidth between AI chips using CoWoS packaging and HBM can reach the TB/s level, an order of magnitude higher than that of traditional packaging, perfectly solving the "memory wall" problem and becoming the standard for high-end AI training chips.

With the accelerating iteration of large models such as ChatGPT, the global demand for cloud AI chips has exploded. The total global demand for CoWoS will increase from 370,000 wafers in 2024 to 670,000 wafers in 2025 and reach 1 million wafers in 2026. This explosive growth has further exacerbated the production capacity gap.

Currently, only a few leading AI chip companies have the strength to "lock in production capacity" on a large scale. The remaining application-specific integrated circuit (ASIC) manufacturers and second-tier AI chip companies are all facing the dilemma of insufficient CoWoS production capacity.

Recently, a Morgan Stanley report predicted that by 2026, NVIDIA's total demand for CoWoS wafers will reach 595,000, accounting for 60% of the global total demand. Of this large order, about 510,000 wafers will be undertaken by TSMC, mainly for the next-generation Rubin architecture chips. Based on this calculation, NVIDIA's chip shipments in 2026 can reach 5.4 million, of which 2.4 million will come from the Rubin platform. Outsourced semiconductor assembly and test (OSAT) manufacturers such as Amkor and ASE/SPIL will also share about 80,000 wafers of CoWoS production capacity for NVIDIA, mainly for its Vera CPU and automotive chips.

Following closely is Broadcom, with an expected demand of 150,000 wafers, accounting for 15% of the total demand. Its production capacity is mainly for custom ASICs for major customers, including 90,000 wafers reserved for Google's TPU (85,000 wafers from TSMC and 5,000 wafers from ASE/SPIL), 50,000 wafers for Meta, and 10,000 wafers for OpenAI.

AMD is expected to obtain 105,000 CoWoS wafers, occupying about 11% of the market share. Among them, 80,000 wafers will be produced at TSMC for its MI355 and MI400 series of AI accelerators.

Other players include Amazon, Marvell, and MediaTek. Amazon has reserved 50,000 wafers through its partner Alchip; Marvell has reserved 55,000 wafers for custom chips for AWS and Microsoft; MediaTek has reserved 20,000 wafers for Google's TPU project.

Overall, the above major customers have locked in more than 85% of TSMC's total CoWoS production capacity, leaving less than 15% for second-tier AI chip manufacturers, dedicated ASIC companies, and startups. With the scheduling generally postponed to 2026 or even later, the scarcity of production capacity has evolved from a technical bottleneck to a market entry barrier.

When CoWoS becomes an exclusive resource for a few giants, a practical question needs to be reconsidered: Is there any other alternative besides CoWoS?

02

Intel's EMIB Launches a Surprise Attack!

Intel's EMIB advanced packaging is becoming one of the alternative solutions for chip companies.

Compared with CoWoS, EMIB has several advantages.

Firstly, the structure is simplified. EMIB abandons the expensive and large-area interposer and directly interconnects the chips using a silicon bridge embedded in the carrier board, simplifying the overall structure and having a higher yield rate than CoWoS.

Secondly, the problem of the Coefficient of Thermal Expansion (CTE) is smaller. Since EMIB only embeds silicon bridges at the edges of the chips, the overall silicon ratio is low. Therefore, the contact area between silicon and the substrate is small, resulting in a smaller problem of CTE mismatch and less likelihood of packaging warpage and reliability challenges.

Finally, EMIB also has an advantage in packaging size. Compared with CoWoS-S, which can only reach 3.3 times the reticle size, and CoWoS-L, which has currently developed to 3.5 times and is expected to reach 9 times in 2027; EMIB-M can already provide 6 times the reticle size and is expected to support 8 to 12 times from 2026 to 2027. In terms of price, since EMIB abandons the expensive interposer, it can provide a more cost-effective solution for AI customers.

However, the EMIB technology is also limited by the silicon bridge area and wiring density. The available interconnection bandwidth is relatively low, the signal transmission distance is longer, and there is a slightly higher latency problem.

Since Intel announced the establishment of an independent foundry service (Intel Foundry Services, IFS) business group in 2021, it has been developing the EMIB advanced packaging technology for many years and has applied it to its own Server CPU platforms such as Sapphire Rapids and Granite Rapids.

Behind the increasing attention to EMIB is the rise of the ASIC solution represented by Google.

It is reported that Marvell and MediaTek have considered including Intel's EMIB advanced packaging as an option in their ASIC chip designs. Google has also decided to introduce Intel's EMIB advanced packaging for trial use in its TPU v9 AI chips in 2027. Apple, Broadcom, and Qualcomm may also soon become customers of Intel's foundry business. The recruitment information of these three companies shows that one of the key requirements for recruiting packaging engineers is to master Intel's EMIB technology, indicating that these companies are eager to recruit engineers familiar with Intel's EMIB technology to support the design of next-generation products.

Among them, Apple focuses on self-developed cloud ASICs, while Qualcomm focuses on Tier 2 AI accelerator card products. Neither of their application scenarios depends on CoWoS packaging. In contrast, EMIB packaging has better cost-effectiveness and can better meet their product requirements. In addition, for ASIC inference scenarios with relatively low computing requirements, EMIB packaging also has the technical support capability.

03

The Fierce Competition Among the Three Giants in Advanced Packaging

The rise of EMIB is dragging the advanced packaging market into a fierce competition among "TSMC, Intel, and Samsung".

Regarding TSMC, it should be noted that most of the major customers of TSMC's CoWoS production capacity in 2026 are American companies. Now, American customers hope to achieve full-industry chain production in the United States, but TSMC and its upstream and downstream partners currently have no available back-end production capacity in the United States.

In the middle of this year, market rumors said that TSMC is vigorously promoting its production plan in the United States, including building a wafer fab, a research and development center, and advanced packaging facilities. In addition to chip manufacturing, advanced packaging technologies such as CoWoS are one of the most critical links in the supply chain. It is reported that TSMC seems to be shifting its strategic focus to this field, planning to start building a packaging factory in 2026, which is expected to be completed and put into production in 2029.

The packaging factory will be located in Arizona, and TSMC has started recruiting CoWoS equipment service engineers. This advanced packaging factory will be responsible for producing CoWoS and its derivative technologies, as well as next-generation packaging solutions such as SoIC and CoW. These technologies will be applied to product lines such as NVIDIA's Rubin series and AMD's Instinct MI400. According to the preliminary plan, the packaging factory in Arizona will be linked with the local wafer fab because products such as SoIC need to use chips with an interposer layer.

American customers still rely on the production capacity in Taiwan, China, for the packaging process. The chips manufactured at TSMC's US wafer fab need to be airlifted to Taiwan, China, for packaging, resulting in a significant increase in the overall cost. Therefore, if the United States does not have local CoWoS manufacturing capabilities, Intel may be a viable option.

Samsung is also taking advantage of the situation to stir up the competition. Samsung's advanced packaging technology system is divided into two major series: 2.5D I-Cube and 3D X-Cube. Among them, X-Cube, as the core of Samsung's 3D packaging, realizes vertical electrical interconnection of chips through TSV technology and is divided into two process paths: bump interconnection and hybrid bonding.

In addition, Samsung Electronics' Advanced Packaging (AVP) department is also leading the development of "semiconductor 3.3D advanced packaging technology", which is targeted for application in AI semiconductor chips and will be mass-produced in the second quarter of 2026. This technology connects logic chips and HBM by installing an RDL interposer instead of a silicon interposer; and stacks logic chips on the LLC through 3D stacking technology. Samsung expects that after the commercialization of the new technology, compared with the existing silicon interposer, the performance will not decline, and the cost can be saved by 22%. Samsung will also introduce the "Panel-Level Packaging (PLP)" technology in 3.3D packaging.

The real variable lies in Intel. At this year's Intel Foundry Forum, Intel announced a new variant of the EMIB technology - EMIB-T, where T should refer to TSV through-silicon via; in addition, there are also Foveros-R and Foveros-B packaging using RDL redistribution layer and Bridge chip respectively. This process for HBM4 and UCIe chip integration builds vertical power channels in the substrate through TSV and M Bridge technology without the need to "detour" like traditional solutions. This means that EMIB-T can achieve lower DC/AC noise, which is beneficial to the stability of signal transmission.

Intel said that EMIB-T supports migration from other 2.5D advanced packaging technologies, and this process does not require major re-design. For future EMIB, Intel predicts that by 2026, it can achieve a total packaging size of about 120mm×120mm through more than 20 EMIB bridges and integrate 12 HBM memory stacks; by 2028, the packaging size will be further expanded to 120mm×180mm, and the number of HBMs will exceed 24.

Amkor, the world's second-largest OSAT company, announced at this year's Intel Foundry Direct Connect conference that it will establish a strategic partnership with Intel. Amkor will adopt the EMIB packaging process in its manufacturing plants in multiple locations to establish an alternative source for EMIB. It is reported that Amkor has decided to build EMIB production capacity at its K5 factory in Songdo, Incheon, South Korea, because the equipment there is sufficient to meet the requirements of the EMIB advanced packaging process, and there are abundant existing materials, components, and human resources.

People familiar with the matter said that the K5 factory in Songdo, Incheon, South Korea, will not only undertake the EMIB packaging of Intel's product department chips but also provide services for external customers of Intel's foundry business. In addition to South Korea, Amkor's manufacturing plants in Portugal and Arizona, USA, will also introduce Intel's EMIB process.

According to Yole data, it is expected that in 2025, the global advanced packaging market will account for more than 51% of the total market for the first time, surpassing traditional packaging, and will continue to grow at a compound annual growth rate (CAGR) of 10.6% to reach $78.6 billion in 2028. The rise of EMIB is breaking the "monopoly" pattern.

Meanwhile, the rise of EMIB does not mean the decline of CoWoS. Instead, it marks a new development stage for the advanced packaging industry, where products are more precisely matched to specific application scenarios. The advantages of CoWoS in interconnection density and ultra-high-frequency signal integrity remain the core requirements of high-end GPU manufacturers such as NVIDIA and AMD and are difficult to be replaced in the short term. On the other hand, EMIB may open up incremental space in fields such as ASICs and mid-range AI chips.

This article is from the WeChat official account "Semiconductor Industry Insights" (ID: ICViews). The author is Feng Ning. This article is published by 36Kr with permission.