Google Crowned the "New King of AI", and the Landscape of Advanced Packaging Changes

North American cloud service providers (CSPs) such as Google and Meta have started actively approaching Intel about the EMIB solution.

As Google ascends to the throne as the "new king," the landscape of computing power chips has also changed with the sudden emergence of TPU. Correspondingly, as a supporting solution for high - performance computing, advanced packaging technology may also begin to transform synchronously.

According to the latest observation by Trendforce, North American cloud service providers (CSPs) such as Google and Meta have started actively approaching Intel about the EMIB solution. The report points out that as Google decides to trial EMIB in TPU v9 in 2027, Meta is also actively evaluating and planning to use it in its MTIA products.

What is EMIB? Simply put, it is a 2.5D advanced packaging technology introduced by Intel. Although TSMC's CoWoS has long dominated this field, EMIB has quietly attracted the market's attention with its own advantages. It is reported that Apple recently released a recruitment requirement for a DRAM packaging engineer, requiring experience in advanced packaging technologies such as CoWoS, EMIB, SoIC, and PoP. The product management director position recruited by Qualcomm for its data center business unit also requires familiarity with EMIB technology.

In addition, it is reported that Marvell Technology, MediaTek, etc. are also considering introducing Intel's EMIB advanced packaging for their ASIC projects. The reason, as Trendforce points out, is that the strong demand for AI HPC (high - performance computing) has led to problems such as CoWoS's shortage of production capacity, limitations on photomask size, and high prices.

Furthermore, behind the increasing attention to EMIB is the rise of the ASIC solution represented by Google. Western Securities points out that Google mainly relies on self - developed TPU on the chip side and has formed a mature ASIC system integrating training and inference. The Gemini 3 model was trained under Google's TPU cluster. The officially released next - generation Ironwood (TPU v7) is specially designed for inference models, demonstrating its engineering advantages in large - scale, low - power inference.

Facing the strong competitiveness of Google's TPU, Dan Ives of Wedbush Securities said that the market is "rediscovering" the huge market for ASIC chips. According to the judgments of multiple institutions, from 2026 to 2027, the number of ASICs of Google, Amazon, Meta, OpenAI, and Microsoft may experience explosive growth.

Against this background, the technical advantages of EMIB are gradually being favored by the market. Trendforce summarized that as cloud service providers accelerate the self - development of ASICs and have an increasing demand for packaging area to integrate chips with more complex functions, some manufacturers have begun to consider switching from TSMC's CoWoS solution to Intel's EMIB technology.

EMIB vs CoWoS: Who will win?

Compared with CoWoS, the advantages of EMIB are mainly concentrated in area and cost.

From a market perspective, CoWoS has undergone continuous iteration for more than a decade and has a high degree of technological maturity. When NVIDIA CEO Jensen Huang was asked whether NVIDIA would use the advanced packaging technologies of Samsung or Intel in the United States, he said that CoWoS is a very advanced technology and NVIDIA currently has no other options. In terms of customers, Trendforce predicts that GPU suppliers such as NVIDIA and AMD, which have high requirements for bandwidth, transmission speed, and low latency, will still mainly use CoWoS as their packaging solution.

The problems faced by CoWoS are also quite obvious. NVIDIA alone occupies more than 60% of its production capacity, squeezing out other customers. In October this year, TSMC said that it is currently in the early stage of artificial intelligence applications, the AI production capacity is very tight, and it is still working hard to increase the CoWoS production capacity in 2026. In addition, the high cost of the large interposer inside CoWoS is also unacceptable to some customers.

In contrast, EMIB, which allows a highly customized packaging layout, is expected to become the best alternative for ASIC. According to the Trendforce report, compared with CoWoS - S, which can only reach 3.3 times the photomask size, and CoWoS - L, which has currently reached 3.5 times and is expected to reach 9 times in 2027; EMIB - M can already provide 6 times the photomask size and is expected to support 8 to 12 times from 2026 to 2027.

In terms of price, since EMIB abandons the high - cost interposer and directly interconnects the chips using a silicon bridge embedded in the carrier board, simplifying the overall structure, it can provide a more cost - effective solution for AI customers.

So far, EMIB is still highly tied to the needs of ASIC customers. Trendforce points out that the EMIB technology is limited by the silicon bridge area and wiring density, so the available interconnection bandwidth is relatively low, the signal transmission distance is relatively long, and there is a slightly higher latency problem. Therefore, currently only ASIC customers are more actively evaluating and negotiating its introduction.

This article is from the WeChat official account "Science and Technology Innovation Board Daily", author: Zhang Zhen. Republished by 36Kr with permission.