In the field of large chip packaging, there are three major players.

In the wave of rapid development of AI chips, high-performance computing (HPC) cores such as GPUs and AI ASICs, as well as HBM (High Bandwidth Memory), are becoming the main force of high-end products adopting 2.5D/3D packaging technologies. Advanced packaging platforms are crucial for enhancing the performance and bandwidth of devices. Their importance has made them the hottest topic in the semiconductor field, even surpassing the previous cutting-edge process nodes.

Recently, the news that Intel's advanced packaging technology, EMIB, is being evaluated by tech giants Apple and Qualcomm has attracted wide attention. Apple is seeking DRAM packaging engineers familiar with technologies such as CoWoS, EMIB, SoIC, and PoP in its relevant recruitment information. Qualcomm is also recruiting a director of data center product management, requiring familiarity with Intel's EMIB technology. Although these actions do not mean that the two chip design giants have officially switched, they clearly indicate that the world's top self-developed chip companies are actively evaluating Intel as a potential alternative to TSMC.

Image source: Qualcomm Incorporated

In the field of advanced packaging for AI chips, TSMC, Intel, and Samsung have formed a "tripartite confrontation" pattern. Due to their different self-positions, these three companies also play different packaging roles in the industrial chain. According to the analysis of Yole Group, in the short term, the revenue from advanced packaging will exceed $12 billion in the second quarter of 2025. Driven by the strong demand for artificial intelligence and high-performance computing, the market performance is expected to be even stronger in the second half of the year. In the long run, the scale of the advanced packaging market was approximately $45 billion in 2024 and is expected to grow at a strong compound annual growth rate of 9.4%, reaching approximately $80 billion by 2030.

TSMC: The Only Answer for GPUs and Ultra-Large-Scale HBM

TSMC's CoWoS (Chip-on-Wafer-on-Substrate) is a 2.5D advanced packaging technology developed by TSMC. It allows multiple chips, including logic chips, memory chips, and analog chips, to be integrated side by side on a high-density silicon interposer.

The CoWoS technology was introduced in the early 2010s. After nearly a decade of continuous iteration, it has become the de facto standard for high-bandwidth packaging globally. Currently, manufacturers using CoWoS include NVIDIA (H100, H200, and GB200 all use CoWoS or CoWoS-L), AMD's MI300 series, Broadcom's AI ASIC, and some acceleration chips from Marvell.

Its maturity is irreplaceable, but its problems are also inevitable.

First, there is a serious shortage of CoWoS production capacity, which has been locked up by NVIDIA for a long time. Foreign media generally estimate that NVIDIA alone occupies more than half of the CoWoS production capacity. UBS predicts that driven by Blackwell, Blackwell Ultra, and Rubin, NVIDIA's demand for CoWoS wafers will reach 678,000 pieces in 2026, a nearly 40% increase from this year. Additionally, it is estimated that by 2026, NVIDIA's total GPU production will reach 7.4 million pieces. With AMD and Broadcom also in the picture, CoWoS has entered an extreme state where the "queuing period > product lifecycle". This means that Apple, Qualcomm, and Broadcom will be in a passive situation of "unable to get in the queue" when evaluating new chip packaging.

According to TSMC's financial report disclosure in the third quarter of 2025, the sales revenue of its high-performance computing (HPC) business remained flat quarter-on-quarter. TSMC emphasized that this does not mean a weakening of AI demand. On the contrary, the actual demand is stronger than the company's expectation three months ago. The main bottleneck for revenue growth lies in the insufficient production capacity of advanced packaging, especially the CoWoS technology, which limits the shipment volume of HPC products.

In response, TSMC is rapidly expanding its CoWoS production capacity. According to Morgan Stanley's estimate, TSMC plans to increase its CoWoS production capacity by more than 20% from the original estimate of 100 kwpm (thousand pieces per month) by the end of 2026. Currently, it is expected that the CoWoS production capacity will reach at least 120 - 130 kwpm.

Second, the cost of the large interposer is extremely high, causing the BOM cost of packaging to skyrocket. The area of the laser interposer in CoWoS is as large as several hundred square millimeters, and although it uses mature nodes such as 65nm/45nm, it is still expensive. In advanced packaging quotes, the interposer often accounts for 50% - 70% of the cost. In some customer cases, "the packaging is more expensive than the chip itself".

CoWoS-S

Third, the more HBM stacks there are, the more difficult it is to manage the thermal density of CoWoS. The HBM stack volume of H200 and GB200 is higher than that of H100, and the hotspots in the packaging area are further concentrated.

Overall, CoWoS is the best choice, but not everyone can afford it, nor can everyone get in the queue. Although TSMC's SoIC (3D stacking) can accelerate development, it exerts great pressure on cost and yield.

Intel's EMIB Becomes Plan B

If TSMC's CoWoS is the "king of high bandwidth", then Intel's combination of EMIB + Foveros is a collection of flexibility, cost structure, and a localized supply chain.

In the past 10 years, industry discussions about Intel have mainly focused on its lag in process nodes, but a fact has been overlooked: Intel is one of the earliest and most aggressive players in advanced packaging. Now, as top chip manufacturers such as Apple and Qualcomm start recruiting "EMIB Packaging Engineers", Intel's packaging technology roadmap has for the first time entered the review window of global mobile phone SoC and large ASIC customers.

So, why EMIB?

EMIB structure diagram (Source: Intel)

EMIB (Embedded Multi-die Interconnect Bridge) is essentially an embedded silicon bridge - it does not cover the entire package but only adds high-density silicon wiring in local areas where high-speed interconnection is required. As shown in the figure below, EMIB places a silicon bridge in the substrate cavity and fixes it with an adhesive; then, a dielectric layer and a metal wiring layer are stacked on top of it. By combining two different bump pitches on the Chiplet, EMIB can achieve cost-effective heterogeneous integration and support ultra-large-scale system expansion.

According to Intel's materials, EMIB is the industry's first 2.5D interconnection solution that embeds a silicon bridge in the package substrate. It has been in mass production since 2017 and has been applied in products in fields such as servers, networks, and high-performance computing.

Compared with CoWoS: In terms of architecture, CoWoS uses a whole large interposer, while EMIB is a small silicon bridge embedded as needed, occupying very little space. Therefore, it does not affect the balance of input/output (I/O) signals and does not damage the power integrity characteristics of the system. This is in sharp contrast to the complete large-area silicon interposer: in the solution using a silicon interposer, all signal and power vias must pass through the interposer, bringing additional impedance and noise. In terms of cost, since the interposer area of CoWoS is large, it is also relatively more expensive. In terms of flexibility, CoWoS has a fixed area and is suitable for large chips, while EMIB is more suitable for customized ASICs and small Chiplets. In terms of heat dissipation, the local interconnection of EMIB actually facilitates heat dissipation.

EMIB also has three key advantages:

It supports ultra-large-scale, heterogeneous die combinations and allows highly customized packaging layouts.

It can achieve high-speed data transmission between adjacent dies while only requiring simple driver/receiver circuits.

It can optimize each inter-die interconnection individually and achieve an optimized design by customizing the bridge structure for different links.

Therefore, EMIB is not designed for "memory bandwidth monsters" like GPUs. Its best stage is for customized ASICs, AI inference chips, base station/network accelerators, SoC-level modular design, UCIe/Chiplet interconnection experimental platforms, etc. That is to say, the value of EMIB is not "stronger" but "more general and more flexible". This is exactly the ability that Apple, Qualcomm, and Broadcom need in their next-generation architecture design.

It is understood that Intel is also continuing to expand its EMIB portfolio. As the demand for higher power supply capabilities continues to increase, Intel integrates metal-insulator-metal (MIM) capacitors into the silicon bridge in its EMIB-M to enhance power transmission capabilities. It has also added through-silicon vias (TSVs) in its EMIB-T solution.

EMIB can be used not only for 2.5D packaging. When EMIB is used in combination with Foveros 2.5D and Foveros Direct 3D, it can form a more flexible EMIB 3.5D solution. Jensen Huang previously publicly praised Foveros, and the industry is not without confidence in its technological maturity.

Evolution of Intel's advanced packaging (Source: Intel)

EMIB 3.5D is a hybrid architecture that combines the silicon-embedded bridging of EMIB and the advanced die stacking process of Foveros in the same package. This hybrid architecture utilizes Foveros' vertical stacking ability and then superimposes EMIB's horizontal high-density interconnection, thereby achieving a better balance among packaging size, computing performance, energy consumption performance, and cost efficiency.

EMIB 3.5D solves many limitations in traditional packaging architectures, including thermal warping, reticle size limits, and interconnection bandwidth bottlenecks. It can significantly increase the available silicon area inside the package and provide greater design space for building highly complex multi-chip systems.

In addition to its technological advantages, Intel's domestic packaging production capacity in the United States has also become a "second supply chain" driven by geopolitics. TSMC's packaging is concentrated in Taiwan (Kaohsiung, Zhunan), and Samsung's packaging in South Korea is concentrated in South Korea/Southeast Asia, while Intel is building an advanced packaging production base in the United States, including Fab 9/Fab 11x in New Mexico, future packaging lines in Ohio, and a packaging R & D line in Lake Forest (California). For the supply chains of domestic cloud providers and AI chip companies in the United States, the advantages of domestic production, high controllability, and non - dependence on East Asian packaging far outweigh simple cost factors.

Therefore, Intel's packaging does not "dominate in technology" but rather in the security of the industrial chain.

Samsung: Reverse Entry into Advanced Packaging from the HBM Supply Chain

Samsung's packaging is more like a "reverse" entry into the key node of the AI era from the HBM supply chain. If Samsung's HBM can fully meet the requirements of leading customers such as NVIDIA, it will have the opportunity to gain greater influence in packaging route selection and even system architecture collaboration by leveraging the supply chain discourse power of HBM.

Samsung's representative advanced packaging technologies are mainly I - Cube (2.5D packaging) and X - Cube (3D packaging), where I - Cube includes two types: I - Cube S/E.

Different from TSMC's CoWoS and Intel's EMIB/Foveros, Samsung's I - Cube technology is designed in reverse from the perspective of an "HBM supplier", so the technological path is significantly different.

Specifically, I - Cube S is a 2.5D solution with a large silicon interposer. The architecture of I - Cube S is almost the same as that of TSMC's CoWoS - S: both use a whole silicon interposer for interconnection, the cost is generally moderately high, and the bandwidth supports HBM3/HBM3E (as shown in the figure below).

I - Cube S (Source: Samsung)

Here, we can review why a large silicon interposer is used. This is mainly because HBM stacking requires extremely high IO density. High bandwidth x multiple channels can cover a large lateral area. Using interposer wiring can be very spacious, the signal integrity (SI) is better, and the power distribution network (PDN) is also more solid, making it more suitable for high - power chips.

I - Cube E is a hybrid low - cost solution that uses a Si Bridge + RDL Interposer. As shown in the figure below, it does not have a whole silicon interposer. Instead, it uses an RDL Interposer (fan - out redistribution interposer), and a Si Bridge Die (small - sized silicon bridge) is used at the lower layer to provide local high - density interconnection, similar to the concept of Intel's EMIB.

I - Cube E

In the field of 3D packaging, X - Cube is a huge leap for Samsung's advanced packaging technology. Its core method uses the method of stacking logic dies on the Z - axis, significantly improving the dynamic bonding ability. With these innovations, Samsung has been able to rapidly promote its Chip - on - Wafer (CoW) and copper hybrid bonding (HCB) technologies. By increasing the chip density of each stack, X - Cube further enhances the speed and performance of the product.

Copper hybrid bonding is the key technology for X - Cube to achieve high - density interconnection. From the perspective of chip layout flexibility, HCB technology has great advantages over traditional chip stacking technologies. Samsung Foundry is actively developing ultra - fine copper hybrid bonding technologies, such as connection specifications below 4 microns, to achieve higher - density 3D stacking.

Summary

Overall, if TSMC's advanced packaging focuses more on high