NVIDIA "mistakenly damaged" a chip
Recently, the alliance between two chip giants, NVIDIA and Intel, has set off a storm in the market.
This strategic alliance, aiming to integrate the advantages of AI accelerated computing and the x86 ecosystem, hinges on the architectural interconnection capabilities of NVIDIA's NVLink technology. This high-speed interconnection solution, once a rival to PCIe, has now gained unprecedented weight and influence with Intel's entry.
Compared with the PCIe standard, which Intel has dominated for over two decades, NVLink offers several times the bandwidth and lower latency, demonstrating overwhelming competitiveness in scenarios such as AI training and supercomputing. This poses an unprecedented challenge to the PCIe technology route.
What's more intriguing is that Intel, the founder of the PCIe standard, has chosen to embrace NVLink, a move with profound symbolic significance. If this "self - innovation" in the technology route proceeds as planned, it not only means a reconstruction of the interconnection paradigm between CPUs and GPUs but may also impact Retimer chips, which have long relied on the demand for high - speed signal compensation in PCIe.
In the wave of technological route reconstruction and substitution triggered by NVLink, the saying "some are happy while others are sad" rings true. NVIDIA has opened up the x86 ecosystem path for AI infrastructure through this cooperation, and Intel has expanded its boundaries in the high - end computing field with customized products. Undoubtedly, they are the "happy" camp. In contrast, PCIe Retimer chips, which have relied on the demand for high - speed signal compensation in PCIe, have become the "sad" party and are the first to face the impact in this industrial iteration.
The Foundation of PCIe Retimer
To understand Retimer chips, we first need to understand the PCIe bus.
As is well - known, the bus is the "road" for data communication between different hardware components on a computer/server motherboard. The amount of data transmitted per unit time is called bandwidth, measured in bits per second. The bus plays a decisive role in the data transmission speed between hardware. As servers have increasingly high requirements for computing speed and latency, computer bus standards are constantly evolving.
Currently, the most mainstream bus is the PCIe protocol (PCI - Express), proposed by Intel in 2001 to replace older bus standards such as PCI, PCI - X, and AGP. The PCIe protocol has developed rapidly in recent years, with its transmission rate doubling approximately every 3 - 4 years while maintaining good backward compatibility.
Especially today, with the explosive growth of AI computing power demand, high - speed data transmission within data centers is facing unprecedented pressure. This has driven the rapid development of the PCIe protocol, advancing from PCIe 3.0 and 4.0 to 5.0 and 6.0, with the transmission rate increasing from 8GT/s and 16GT/s to 32GT/s and 64GT/s.
However, as the communication rate increases with each generation, the signal attenuation problem becomes more severe. In the iteration of the PCIe standard, on one hand, the development of applications drives the continuous update of the PCIe standard, doubling the speed. On the other hand, since the physical size of servers is limited by industrial standards and has not changed significantly, the insertion loss of the entire link has increased from 22dB in the PCIe 3.0 era to 28dB in the PCIe 4.0 era and further to 36dB in the PCIe 5.0 era. Solving the insertion loss problem of the PCIe signal link and increasing the PCIe signal transmission distance are important challenges in the industry.
The emergence of Retimer chips is an inevitable result of the development of PCIe to a certain stage. Before PCIe 4.0 and earlier versions, the data transmission rate was relatively low, and the requirements for signal integrity were not high. However, in the PCIe 5.0 and 6.0 eras, with the data transmission rate increasing to 32GT/s and 64GT/s, signal attenuation and jitter problems have become more prominent, and the insertion loss has also increased.
The PCIe specification has a precise insertion loss budget. For example, the insertion loss budget for the PCIe 6.0 version is 32dB, meaning that the total signal loss during transmission must be kept within 32dB to maintain signal quality.
To address this, PCIe Retimer chips have become the mainstream solution for signal attenuation problems.
A Retimer chip is a mixed - signal analog/digital chip. Its principle is to use an internal clock recovery circuit to re - time the input signal, eliminating clock skew and jitter and correcting the phase and time deviation of the signal. It can extend the transmission distance of the interface and improve signal quality. PCIe Retimer chips mainly solve problems such as inconsistent signal timing, high loss, and poor integrity during high - speed and long - distance data transmission in data centers and servers using the PCIe protocol.
Internal structure of a Retimer chip (Source: PCI - SIG official website)
Compared with other technical solutions in the market, the current Retimer chip solution has certain comparative advantages in terms of performance, standardization, and ecosystem support. It's worth noting that Retimer chips can flexibly switch between PCIe and CXL modes, making them more in line with the future CXL interconnection trend.
This feature gives it high value in the general server and AI server markets.
In the general server field, with the expansion of cloud computing and big data centers and the rapid increase in the penetration rate of PCIe 5.0 and higher - version servers, each server needs to be equipped with 2 - 4 Retimer chips (for connecting CPUs to PCIe slots and high - speed storage). Coupled with the growth of edge - computing servers, the market demand is increasing exponentially.
Moreover, with the rise of the AI wave, AI servers have become one of the main incremental application scenarios for Retimer chips.
It is understood that the number of PCIe Retimer chips in an AI server is directly related to the number of GPUs configured in the server. This is because the number of lanes in a GPU directly determines the ratio of the PCIe link.
AI servers usually require multiple GPUs to work together. A single AI server often has 4 - 8 or even more GPUs. The PCIe links between GPUs and CPUs and between GPUs are not only long but also need to transmit a large amount of training data simultaneously. Retimer chips are the key to solving the "signal bottleneck in multi - GPU interconnection," significantly improving the collaborative efficiency of AI computing clusters.
Currently, a typical mainstream AI server with 8 GPUs requires 8 or even 16 PCIe 5.0 Retimer chips.
Evidently, Retimer chips have a vast market space in the AI era and the server field.
Two Oligarchs Leading and Multiple Competitors in the "Golden Track"
In the golden age of PCIe high - speed interconnection, the Retimer chip market has formed a pattern of "two oligarchs leading and multiple competitors vying."
Currently, the global market is mainly divided between server analog - digital chip manufacturers and traditional analog giants. The competition between AsteraLabs and Montage Technology is particularly notable. AsteraLabs, with its first - mover advantage in PCIe 5.0, holds a major global share, while Montage Technology is rapidly rising as a domestic alternative. Together, they dominate the high - end market. Pericom and IDT (acquired by Renesas) hold their traditional positions based on their technological accumulation, while giants like TI and Microchip cover the mid - to low - end fields with general - purpose products, creating a multi - level competitive ecosystem.
Looking back at the development history, different manufacturers have distinct technological paths.
As an early entrant in the market, Pericom, with its first - mover advantage in the PCIe 3.0/4.0 era, was the first to have its products certified by mainstream platforms such as Intel and AMD, becoming a core supplier to server manufacturers. It has now developed a complete product line covering PCIe 3.0 - 5.0, with its chips' transmission rate and low - latency characteristics firmly establishing its position in the high - end market.
IDT, relying on its technological accumulation in timing chips, had an advantage in multi - generation PCIe protocol compatibility in the early days. After being acquired by Renesas, its Retimer technology has been deeply integrated with Renesas' analog chip capabilities and continues to expand into the PCIe 5.0/6.0 fields.
The US - based AsteraLabs has broken the traditional mold with its "Smart Retimer" concept. Its PCIe 4.0 products were mass - produced in 2024, and its PCIe 5.0 products reduce customer upgrade costs through pin - compatible design. By establishing the Cloud - Scale Interop Lab ecosystem with cloud service providers, it has quickly captured the AI server market and become the dominant player in the 4.0/5.0 era.
Montage Technology, the domestic leader, has demonstrated strong substitution capabilities. After entering the market from the memory interface chip field, its PCIe 4.0 Retimer chips are in stable mass production. The shipments of its PCIe 5.0 products have doubled for two consecutive quarters since 2024, with a full order backlog. In early 2025, it was the first to launch PCIe 6.x/CXL 3.x Retimer chips and send samples, with a transmission rate of 64GT/s, continuously strengthening its technological barriers.
Traditional analog giants have adopted differentiated strategies to capture market share. TI, with its extensive industrial customer base, provides general - purpose Retimer chips suitable for multiple scenarios. Although it is not focused on the high - end AI field, it remains competitive in mid - to low - speed PCIe links. Microchip released a Retimer series supporting PCIe 5.0 and CXL 2.0 as early as 2020, and its products have become a common choice for Intel platform reference designs, holding a place in the traditional server market.
With the dual dividends of domestic substitution and technological upgrading, the competition in the high - speed interconnection field is entering an opportunity period.
Industry data predicts that the global market size of PCIe Retimer chips will reach $1.8 billion in 2025. Given this market potential, Retimer chips have been regarded as a "must - have component in the wave of PCIe high - speed development" and a "golden track" in the semiconductor industry, deeply linked to AI computing power and server expansion.
The nvtel Alliance Brings Subtle Changes
However, the technological revolution initiated by the alliance between NVIDIA and Intel may bring subtle changes to the PCIe Retimer market.
When NVIDIA strategically invested $5 billion in Intel and opened up its NVLink technology ecosystem, this long - time challenger to the PCIe standard finally obtained the key leverage to reshape the industrial landscape. And Intel, the founder of the PCIe protocol, choosing to "defect" has given this impact the profound power to disrupt the technological camp.
First, the overwhelming effect of the technological gap is immediate. The fifth - generation NVLink technology has achieved a total bandwidth of 1.8TB/s, more than 14 times that of PCIe Gen5, and has minimized signal transmission loss through chip - level integrated design. This advantage directly undermines the value of PCIe Retimer chips. For example, in NVIDIA's GB200 NVL72 rack system, 576 GPUs form a global bandwidth of over 1PB/s through NVLink, enabling stable interconnection without any signal compensation chips. In contrast, in the traditional solution, an 8 - GPU AI server needs to be equipped with 8 - 16 PCIe 5.0 Retimer chips to avoid signal distortion.
NVLink provides the x86 architecture with higher - bandwidth and lower - latency interconnection capabilities than traditional PCIe, which may change the computing and data flow patterns within data centers.
When Jensen Huang emphasized at the press conference that "the best CPU and the best GPU should be combined through NVLink," he actually declared the end of the "compensation era" in the high - speed interconnection field.
What's more fatal is that NVIDIA's GPUs have absolute dominance in the AI era, holding 92% of the discrete graphics card market and 24% of the PC GPU market. AI training scenarios almost entirely rely on its chips. In the data center field, customized NVLink x86 CPUs will replace the general PCIe interface solution. In the personal computing field, Intel's SoC integrating RTX GPU dies will reduce the reliance on discrete PCIe graphics cards.
On the other hand, the main function of Retimer chips is "signal amplification." When the PCIe signal attenuates during long - distance transmission, the Retimer receives, reconstructs, and re - transmits the signal to ensure data integrity. When servers adopt a modular design with CPUs and GPUs on different boards, long - distance signal transmission must rely on Retimer chips. If CPUs and GPUs are on the same large motherboard with a shorter signal link, the usage of Retimer chips will decrease.
In short, when developers optimize the software stack around NVLink and cloud service providers deploy NVLink clusters in large quantities, the living space of PCIe Retimer chips will be systematically squeezed.
Moreover, the chain reaction of ecosystem migration is even more destructive. Intel will customize x86 CPUs for NVIDIA, and these chips will directly integrate NVLink interfaces into the AI infrastructure platform. This means that part of the PCIe server market will shift to the NVLink architecture.
Previously, although NVIDIA had some success in promoting a proprietary protocol against the open PCIe alliance, it was ultimately difficult to succeed alone. In this grand game, Intel is the most crucial and subtle "piece." Once Intel's server CPUs support NVLink, the entire server ecosystem will be forced to follow, greatly accelerating the popularization of NVLink and de facto establishing it as an industry standard.
If this solution is successfully implemented, it's easy to imagine that future AI server designs, motherboard layouts, and chip interfaces will all revolve around NVLink. Any chip (whether a CPU or other AI chips) that wants to access this high - performance computing ecosystem must be compatible with the NVLink Fusion protocol. This will create a powerful bundling effect, locking the entire industrial chain, from motherboard manufacturers and server vendors to end - users, firmly within NVIDIA's ecosystem. Once NVIDIA gains control of the protocol, it can profit from every piece of hardware accessing its ecosystem through licensing and certification, becoming the "Qualcomm" of the data center era.
At first glance, NVIDIA's investment in Intel may seem like an overture or infiltration from the GPU hegemon to the CPU giant, aiming to complete its map in the general computing field. However, this is not just an investment but a far - reaching layout to reshape the underlying protocol of future data centers and build NVIDIA's second "moat" besides CUDA, an early - stage layout for the NVLink interconnection protocol.
The essence of this impact is a paradigm shift in the industrial standard from "general compatibility" to "vertical integration." When the leading CPU and GPU manufacturers directly define the interconnection protocol, the value of third - party Retimer chips naturally declines significantly, and the reshaping of the market pattern may already be on the horizon.
From another perspective, the cooperation between NVIDIA and Intel also has advantages in strategic synergy. Facing common challenges (such as the encroachment of the ARM architecture in the server market and AMD's expansion in the CPU and GPU fields), Intel and NVIDIA can form an "nvtel alliance" of "CPU + GPU/interconnection" to jointly define the architecture of the next - generation computing platform.
Conclusion
Overall, when NVIDIA invested in Intel with its NVLink technology and used the strategy of "protocol - defined moat" to reshape the high - performance computing architecture, the PCIe Retimer market has bid farewell to the past golden age of "uninterrupted high - speed growth." The interconnection revolution initiated by these two chip giants may temporarily affect Retimer chips that have relied on the PCIe link.
However, this is just a preliminary view. In the eyes of many analysts, the market space for PCIe Retimer chips still lies in many scenarios that NVLink cannot fully cover. In long - distance transmission and complex topologies, such as the copper cable connections between the head and tail of GPU servers and between GPUs and switches, Retimer chips are still needed to counteract signal attenuation with their adaptive equalization capabilities. In the field of non - GPU device interconnection, especially in complex wiring scenarios, Retimer chips are still crucial for ensuring "zero packet loss" in the high - speed links between SSDs, network cards, and CPUs. Not to mention servers using the OAM architecture, whose general baseboard (UBBP) design naturally relies on Retimer chips to maintain signal