Domestic manufacturers are entering the next-generation storage technology: 3D DRAM
With the explosive growth of artificial intelligence applications such as ChatGPT, the global demand for computing power is climbing exponentially. However, the development of artificial intelligence not only relies on high - performance computing chips but also depends on the coordinated cooperation of high - performance memory.
Traditional memory has difficulty meeting the data transfer speed requirements of AI chips. High - bandwidth memory (HBM), with its innovative stacked design, has successfully overcome three key problems: bandwidth bottlenecks, excessive power consumption, and capacity limitations, providing important support for the efficient operation of AI applications.
However, today, traditional HBM is limited, and 3D DRAM can provide higher bandwidth and further optimize power consumption performance. Global storage manufacturers generally regard 3D DRAM as the key direction for the next - generation memory technology to break through the bandwidth bottleneck.
01
3D DRAM: The Next - Generation DRAM Storage Technology
As the process shrinkage of traditional planar DRAM is gradually approaching the physical limit, 3D DRAM has emerged as a new direction for the development of DRAM storage technology.
The storage units of traditional DRAM adopt a flat design, which greatly limits the improvement of storage density. Through the innovative way of vertically stacking storage layers, 3D DRAM can integrate more storage units within the same space, significantly increasing the storage capacity without increasing the chip area.
As the DRAM process technology continues to shrink, problems such as current leakage and signal interference are becoming more and more serious. Especially in the manufacturing of DRAM below 16nm, there are huge technical challenges. 3D DRAM, with its unique architecture of vertically stacking storage units, realizes the efficient use of limited area and effectively alleviates the dilemma brought by process shrinkage.
It should be noted that HBM belongs to stacked - chip memory, which is fundamentally different from single - chip memory such as 3D NAND flash memory. If a single - chip 3D DRAM chip can be applied in the HBM architecture, it is expected to bring an immediate improvement in storage performance.
02
The 4F² Structure Is the Key Breakthrough, and Industry Giants Are Competing to Layout
Leading DRAM manufacturers continue to promote the upgrade of DRAM processes. However, in the planar structure, further shrinkage of the process is approaching the limit. At this time, the emergence of 3D DRAM has become the key to breaking through the bottleneck. To achieve efficient use of limited area, the layout of storage units must break the traditional horizontal arrangement mode. The core development paths are mainly divided into two categories: One is to verticalize the storage unit structure to significantly compress the space occupation; the other is to learn from the stacking logic in the construction field to achieve a three - dimensional arrangement of the storage unit array.
As a key technical solution for verticalizing storage units, the 4F² structure transforms the traditionally horizontally distributed source, gate, and drain into a vertical hierarchical structure, reducing the area of a single storage unit by about one - third and laying a solid foundation for the high - density integration of DRAM.
The 4F² describes the storage unit area with the minimum feature size F. This way of expression is similar to the track metric of the standard logic unit height (such as the "6T unit"). In DRAM, the minimum feature size usually refers to the width of the word line or bit line, or the spacing between them. As a simple way to represent the storage unit layout density, 4F² facilitates the comparison between different technical solutions. Theoretically, the size of a 4F² unit is only two - thirds of a 6F² unit, which means that without reducing the minimum feature size, the storage density is expected to increase by 30%. However, it should be noted that the expansion of storage density is not only affected by the unit layout but also restricted by many other factors. Therefore, the actual density improvement may be lower than the ideal 30%.
The 4F² unit is the theoretical limit of a single - bit unit. To understand this, it is necessary to clarify that the feature size can refer to either the line width or the spacing between lines (i.e., the half - pitch). In the pattern composed of line width and spacing, the spacing is actually 2F instead of F. It can be seen that the smallest possible size of a single - bit unit is 4F², not simply F². This means that once the 4F² architecture is realized, the horizontal expansion of DRAM can only rely on reducing the minimum feature size F itself. However, in terms of the current technological development, the difficulty of reducing F is increasing rapidly, and it may even become completely infeasible in the future.
In the research and development of the 4F² technology architecture, industry giants are making efforts. Samsung is actively developing vertical channel transistor (VCT) DRAM, and SK Hynix is fully promoting vertical gate (VG) DRAM. Both take 4F² as the core technical architecture. Micron's NVDRAM (where NV stands for non - volatile) made its debut at the International Electron Devices Meeting (IEDM) in 2023 and attracted attention again at the 2025 Symposium on VLSI Technology and Circuits (VLSI 2025). This NVDRAM adopts the 4F² architecture, combining ruthenium word lines and ferroelectric (HZO) DRAM technology with a CMOS bottom array, showing unique technical advantages.
In addition to traditional chip giants, emerging enterprises are also actively exploring the 3D DRAM field. NEO Semiconductor announced the launch of a new technology aiming to completely change the current development pattern of DRAM memory. The company has launched two new 3D X - DRAM unit designs, namely 1T1C (single - transistor single - capacitor) and 3T0C (three - transistor zero - capacitor). According to the plan, NEO Semiconductor is expected to produce a proof - of - concept test chip for 3D X - DRAM in 2026. The storage capacity of this chip is expected to reach 10 times that of the current ordinary DRAM module, greatly improving the storage capacity of DRAM.
Moreover, NEO Semiconductor also said that based on 3D X - DRAM technology, it can produce a 128Gbit DRAM chip with 230 layers, and its storage density is 8 times that of the current DRAM. Against the background of the continuous development of artificial intelligence applications, the demand for high - performance, large - capacity storage semiconductors in the next wave of AI applications (such as ChatGPT) will increase significantly, and 3D X - DRAM technology is the key to meeting this demand.
Furthermore, based on 3D X - DRAM technology, NEO Semiconductor has also developed the world's first X - HBM architecture. This architecture realizes a 32K - bit data bus and a storage capacity of 512Gbit. Its bandwidth and storage density reach 16 times and 10 times that of the existing memory respectively, successfully breaking through the bottleneck of traditional HBM technology and providing ultra - high - bandwidth and large - capacity storage support for AI chips, further promoting the development of artificial intelligence technology.
03
3D DRAM Is Getting Closer to Reality! Breakthrough in Deposition Technology
Recently, researchers from the Interuniversity Microelectronics Centre (IMEC) in Belgium and Ghent University jointly published a paper, announcing that they had successfully grown 300 alternating layers of silicon (Si) and silicon - germanium (SiGe) on a 120 - millimeter wafer. This achievement marks a key progress in the research and development of 3D DRAM, bringing 3D DRAM one step closer to commercial application.
The challenge starts with lattice mismatch. The atomic spacings of silicon and silicon - germanium crystals are slightly different. Therefore, when stacked, each layer naturally wants to stretch or compress. You can imagine it as trying to stack a deck of cards, where the second card is slightly larger than the first. If not carefully aligned, the stack will twist and topple. In semiconductor terms, these "topples" appear as dislocations, which are tiny defects that may damage the performance of the storage chip.
To solve this problem, the research team carefully adjusted the germanium content in the SiGe layer and tried to add carbon, which acts like a subtle glue to relieve stress. They also maintained an extremely uniform temperature during the deposition process because even a tiny hot or cold spot in the reactor can lead to uneven growth.
04
3D DRAM Reduces Dependence on Lithography Equipment, Highlighting China's Advantages
It is understood that Samsung's VCT DRAM is expected to launch physical products in the next two to three years at the earliest and officially enter the market. In 2024, SK Hynix demonstrated a 3D DRAM prototype with a 5 - layer stacked structure, and its yield rate reached 56.1%, showing a good industrialization prospect. Micron has an advantage in the field of 3D DRAM patents, owning a large number of patents. Its technical path is mainly to innovatively design the shapes of transistors and capacitors without changing the placement of storage cells (Cells).
It is worth noting that in the 3D DRAM process flow, the patterning steps are greatly simplified, and the high - difficulty etching/deposition processes are significantly increased. Two - dimensional NAND was once the main battlefield for the lithography accuracy competition, and its demand for planar shrinkage of storage units far exceeded that of DRAM and logic chips. However, after shifting to a three - dimensional architecture, NAND achieves a density leap through the number of stacked layers, and the importance of high - aspect - ratio etching is highlighted. Under the trend of 3D DRAM, the industrial value is migrating from lithography equipment to the etching and deposition links.
Currently, Chinese mainland is restricted in terms of lithography equipment resources, and the technical characteristics of 3D DRAM happen to make it less dependent on lithography equipment. This feature provides favorable conditions for the development of the Chinese mainland in the 3D DRAM field. In the research and development of key equipment, domestic enterprises have made important progress. AMEC has successfully developed an etching equipment with an aspect ratio of 90:1, which can meet the demand for high - precision etching in the 3D DRAM manufacturing process and provides important equipment support for the development of the domestic 3D DRAM industry.
In addition, in 4F² and 3D DRAM, an important technology is to vertically stack the control circuits (peripheral circuits, such as sense amplifiers, WL drivers, decoders, etc.). To further reduce the chip area, the wafer with the DRAM cell array and the wafer with the control circuit need to be fabricated separately and then bonded by wafer - to - wafer (W2W) bonding. Domestic bonding equipment manufacturers such as Qinghe Jingyuan have broken through technologies such as hybrid bonding and room - temperature bonding.
Correspondingly, domestic storage manufacturers are also actively deploying technologies related to 3D DRAM. Leading storage manufacturers have patents for DRAM with the Xtacking architecture. According to the query on the website of the National Intellectual Property Administration, as early as 2020, they applied for a patent for DRAM with the Xtacking architecture. The Xtacking architecture is a unique architecture for producing 3D NAND memory, which uses a three - dimensional wafer hybrid bonding process. According to the patent description, the DRAM memory with the Xtacking architecture includes a first wafer with array transistors formed therein, a second wafer with a capacitor structure formed therein, and a bonding interface including multiple bonding structures formed between the first wafer and the second wafer.
Currently, the research and development of 3D DRAM is being promoted simultaneously around the world. Chinese chip manufacturers have great potential to become potential disruptors in the 3D DRAM field because domestic enterprises have a strong motivation to develop 3D technology. The characteristic that 3D technology does not rely on advanced lithography technology is highly compatible with the current development environment of the semiconductor industry in China, which is expected to help China occupy a more favorable position in the global competition of storage chips.
This article is from the WeChat public account "Semiconductor Industry Vertical and Horizontal" (ID: ICViews), author: Pengcheng. Republished by 36Kr with authorization.