They are all eyeing the intermediary layer.
In recent years, the term "Interposer" has frequently appeared in the public eye. The interposer is responsible for carrying and interconnecting core chips such as GPUs and storage devices. Originally, it was not very prominent. However, nowadays, whether it's material companies, equipment companies, or industry giants like TSMC and NVIDIA, all have their eyes on the interposer.
On one hand, there is the JOINT3 alliance led by Resonac, which has gathered 27 global giants in materials, equipment, and EDA, targeting panel - level organic interposers. On the other hand, NVIDIA has sparked a trend of SiC interposers, and Taiwanese manufacturers are increasing their investment, trying to break the limits of power consumption and heat dissipation. These two trends reflect a fact: the interposer has transformed from a "behind - the - scenes supporting role" to the focus of competition among the upstream and downstream of the industrial chain.
What is an interposer?
In recent years, as Moore's Law has slowed down, the difficulty and cost of further miniaturizing single - chip continue to rise. The industry has started to shift towards heterogeneous integration: combining logic chips, memory chips, I/O modules, and even analog chips to form a system - in - package (SiP). To reliably interconnect these "chiplets", a platform with ultra - high wiring density and electrical performance is required - this is where the value of the Interposer lies.
An Interposer is an intermediate layer structure located between the chip (logic/memory) and the package substrate. In advanced packaging, it plays the role of a "bridge" - tightly connecting logic chips (CPUs, GPUs, AI accelerators) with memory chips (HBMs), and is responsible for high - density interconnection, power distribution, and signal transmission.
In short, it is like a "load - bearing floor + circuit hub", enabling multiple chips to be efficiently integrated together like building blocks, thereby achieving higher bandwidth, lower latency, and higher computing power density.
The above figure is a typical 2.5D packaging schematic diagram of a silicon interposer. In the figure, the Silicon Interposer provides high - density interconnection between chips (A1, A2). (Image: Semiwiki)
Currently, there are mainly two types of interposers in mass production: Silicon Interposer (also known as inorganic interposer) and Organic Interposer, also called RDL (Redistribution Layer).
The silicon interposer emerged relatively earlier. Around the late 2000s - early 2010s, TSMC first proposed and mass - produced the CoWoS (Chip - on - Wafer - on - Substrate) process, using a silicon interposer + TSV (Through - Silicon Via) to achieve high - bandwidth interconnection between GPUs and HBMs. In 2012, the Virtex - 7 FPGA produced by TSMC for Xilinx was commercially launched, becoming the first product in the industry to widely use silicon interposers and laying the foundation for the silicon interposer in high - performance computing packaging.
In the mid - 2010s, with the development of Fan - Out packaging (such as InFO, FOPLP), the industry began to explore using organic materials for the redistribution layer (RDL) to replace silicon. There are mainly three reasons behind this: the high manufacturing cost and limited yield of silicon interposers; the increasing size of AI/HPC chips, resulting in serious losses during silicon wafer cutting; and the market's need for a more economical large - scale mass - production solution.
Therefore, organic interposers gradually came into the industry's view. Their advantage lies in relatively simple processes, low material and equipment costs, and significantly lower overall production costs compared to silicon interposers. The disadvantage is the lack of wiring fineness, with larger line widths and line spacings, making it difficult to support extremely high - density interconnections.
Thus, the industry began to explore interposer solutions using other materials.
JOINT3: 27 Giants Target Panel - Level Organic Interposers
On September 3, 2025, Resonac announced on its official website the establishment of the "JOINT3" alliance consisting of 27 members to jointly develop next - generation semiconductor packaging. These 27 members cover almost the entire semiconductor packaging industry chain: from Applied Materials, Lam, and TEL, to Synopsys, Canon, and Ushio, and then to 3M, AGC, Furukawa Electric, etc.
Companies participating in JOINT3 (Source: Resonac)
The alliance will set up the "Advanced Panel - Level Interposer Center (APLIC)" in the Shimodate Factory (Minami - Yuki) in Yuki City, Ibaraki Prefecture, Japan, as the main hub for this project. APLIC is planned to start operations in 2026, focusing on the development of 515×510mm panel - level organic interposers.
So, why did they target organic interposers? The main reason is the bottleneck of silicon interposers: the traditional method is to cut rectangular interposers from 300 mm wafers. As the size of the interposer increases, the geometric loss of "cutting a circle into a square" rapidly magnifies, the number of cuttable pieces per unit area decreases, and the waste at the corners + the number of step - and - repeat exposures increase → the cost per unit of good products rises. The advantage of organic interposers is that panel - level production can significantly improve capacity utilization and reduce costs.
In comparison, the area of a 300 mm wafer is approximately 70,685 mm². The target of the JOINT3 panel - level is 515 × 510 mm ≈ 262,650 mm², and the area of a single panel is about 3.7 times that of a 300 mm wafer. This means that under the same defect density, the "effective patterning area" of the panel - level is significantly larger, which is more friendly to large - size interposers.
(Source: Resonac)
Market demand is another major incentive. As the demand for 2.5D/3D packaging soars, the stacking of AI/HPC chips + HBMs has become the mainstream, calling for interposers with larger areas and higher interconnection densities.
As the leader of the JOINT3 alliance, Resonac will propose research and development priorities, manage the operation of the prototype production line, and promote the overall progress of the project. Resonac will also promote the development of materials optimized for panel - level organic interposers through joint innovation with participating companies.
Hidehito Takahashi, CEO of Resonac, said bluntly: "JOINT3 has brought together world - class companies from various fields. By integrating the complementary advantages of each company, we can jointly tackle challenges in areas that were previously out of reach." This statement reveals two key signals: 1) Industrial collaboration: It is difficult for a single company to make independent breakthroughs, and an alliance is necessary to promote "de facto standards". 2) Strategic intention: Japan hopes to regain its voice in advanced packaging, which is the "second battlefield in the post - Moore era".
From JOINT (2019) to JOINT2 (2021), then to US - JOINT (2023) targeting North American customers, and now to JOINT3 (2025), Resonac is trying to build a cross - national and cross - sector "collaborative research platform" for advanced packaging:
The first - generation JOINT focused on packaging materials, inviting Japanese equipment and material manufacturers to jointly verify the feasibility of organic carriers, redistribution, and resin systems;
JOINT2 included more overseas companies and expanded the verification scope to the process and design aspects;
US - JOINT targeted the US market and emphasized collaboration with application parties (EDA and design companies);
JOINT3 set its goal on panel - level organic interposers for the first time and established a dedicated research and production center (APLIC), allowing alliance members to jointly test and make improvements under a unified production line and standards.
This is reminiscent of TSMC's CoWoS/SoIC - but the difference is that TSMC follows a vertically integrated Foundry - driven approach, while JOINT3 follows a horizontally integrated alliance - driven approach. These two models will form an interesting contrast in the future.
SiC Interposers: A New Direction?
While Japan is busy promoting organic interposers, the Taiwanese supply chain has heated up due to silicon carbide interposers. The origin of the industry rumor is NVIDIA's next - generation Rubin GPU.
According to some sources, Rubin is evaluating replacing the traditional silicon interposer with a SiC interposer for the interconnection between the GPU and HBM to further improve performance. Although there is no official confirmation yet, this direction has become a hot topic in the industry as a future solution.
What are the reasons behind this? There are mainly three points:
Approaching the power consumption limit: The design power consumption of future high - performance chips may exceed 1000V. In contrast, the fast - charging voltage of Tesla is only 350V. Such extreme current poses unprecedented challenges to the carrying capacity of the interposer.
Prominent heat dissipation bottleneck: The heat conduction ability of silicon is limited, making it difficult to meet the heat management requirements under such extreme current. The thermal conductivity of SiC even exceeds that of copper, which can significantly relieve the high - heat pressure during chip operation.
Forced by architectural requirements: Rubin will still rely on NVLink technology, which requires the GPU and HBM to be as closely coupled as possible to achieve maximum bandwidth and minimum latency. SiC, with its superior insulation and heat dissipation properties, becomes almost the only solution.
However, the silicon carbide here is different from the substrates commonly used in automotive power devices. It must be single - crystal silicon carbide with high insulation, which also brings new process challenges:
Extremely high cutting difficulty: The hardness of silicon carbide is close to that of diamonds. Cutting with traditional methods easily results in wavy patterns. Japan's DISCO is developing a special laser cutting machine.
Limited large - size manufacturing: To be compatible with silicon processes, wafers must reach 12 inches or more. However, most Chinese manufacturers are still at the 6/8 - inch stage, with limited mass - production capabilities.
Therefore, the industry generally believes that the first - generation Rubin products will still use silicon interposers, but at the latest, silicon carbide interposers will enter advanced packaging the year after next.
This implies two major trends: Firstly, material crossover - silicon carbide is expected to leap from automotive power devices and enter the top of the AI/HPC chip pyramid for the first time. Secondly, industrial differentiation - if the R & D alliance led by TSMC first overcomes the large - size and process challenges, it may widen the generational gap with mainland Chinese manufacturers.
The Competition Among Three Types of Interposers
If advanced packaging is compared to a relay race, the interposer is the crucial "baton". The choice of different materials determines the balance point of performance, cost, and mass production.
Silicon Interposer
Advantages: Mature processes and clear technical paths. It is already the mainstream solution for 2.5D/3D packaging such as TSMC's CoWoS and Intel's EMIB. It has rich experience in sub - 10µm interconnection and multi - layer TSV (Through - Silicon Via) processes.
Disadvantages: As the packaging area of GPU + HBM continues to increase, the "geometric loss" problem of silicon wafers becomes increasingly prominent, resulting in a decrease in capacity utilization and a sharp increase in costs. At the same time, the limited thermal conductivity of silicon has become a bottleneck for high - power - consumption AI chips.
Organic Interposer
Advantages: Panel - level production (PLP) can be adopted, significantly improving capacity utilization and single - chip size utilization and reducing costs. The material formula is flexible, and the number of layers and wiring can be customized according to system requirements, making it suitable for large - scale AI training chips and HPC packaging.
Disadvantages: There is a difference in the coefficient of thermal expansion (CTE) between the material and silicon, and the problems of warping and reliability still need long - term verification; the electrical performance is somewhat inferior to that of silicon.
SiC Interposer
Advantages: Excellent thermal conductivity, even exceeding that of copper, capable of withstanding the extreme current and power consumption requirements of future AI/HPC chips, and is the key material to break through the heat dissipation bottleneck. It also has good electrical insulation, supporting closer integration of GPU + HBM.
Disadvantages: Extremely high manufacturing difficulty - close to the hardness of diamonds, with a complex cutting process; it must achieve a large - size wafer of ≥12 inches to be compatible with silicon processes, and the industrial chain is still working on this. Capacity and cost are still major challenges.
In terms of trends, in the short term (1 - 2 years), silicon interposers will still be the market mainstream, supporting the mass production of AI/HPC. In the medium term (3 - 5 years), organic interposers will be widely adopted in HPC and AI training chips due to their cost and scale advantages. In the long term (more than 5 years), once the mass - production bottleneck of silicon carbide interposers is broken, they may become the standard configuration for the most advanced AI/HPC packaging.
Conclusion
As the miniaturization of Moore's Law slows down, advanced packaging has become the "second battlefield" in the semiconductor industry. In this battle, the interposer is redefining the ceiling of packaging.
Japan's JOINT3 represents the path of "collaboratively creating standards"; the SiC interposers promoted by NVIDIA are a typical example of "application - driven new materials". These two paths lead to the same goal - ultimately pointing to the fact that the interposer will determine the performance limit of future AI chips.
This "material war" over interposers is far from over. Silicon, organic, and silicon carbide each have their own advantages and disadvantages. In the next decade, they will most likely form a pattern of division of labor and complementarity.
This article is from the WeChat public account "Semiconductor Industry Observation" (ID: icbank), author: Du Qin DQ, published by 36Kr with authorization.