China's FlipFET technology, revolutionizing chips.

In 2025, the semiconductor industry officially entered the GAA era.

With the implementation of GAAFET technology, the aura of "the next big trend in logic chips" has faded.

Samsung has applied GAAFET technology in its 3nm chips, and TSMC has also stated that it will apply GAAFET technology in its 2nm chips to be mass - produced in the second half of this year.

So, after GAA, who will take over? According to the previous technological roadmap, CFET was originally recognized as the benchmark for the next - generation architecture. However, with the opening of VLSI 2025, the FlipFET technology proposed by Peking University in China has caused a greater sensation.

After GAA, who will take over?

For more than half a century, the semiconductor industry has relied on a simple formula: shrink the transistor size, pack more transistors onto each wafer, and then watch the performance soar and the cost plummet.

In the era of 2D transistors, FinFET was the leader.

Before that, it was MOSFET. However, when the gate length approached the 20nm threshold, the ability to control the current declined sharply, and the leakage rate increased. Traditional planar MOSFET officially reached the end.

In 2011, Intel was the first to commercialize FinFET technology and apply it to the 22nm process, significantly improving performance and reducing power consumption. Subsequently, manufacturers such as TSMC and Samsung followed, and FinFET technology shone brightly. Later, in order to improve transistor performance and further reduce the area, the FinFET architecture was continuously improved. Since the 16/14nm process, FinFET has become the mainstream choice.

After entering the 5nm process, FinFET began to face challenges such as fin stability, gate width limitation, and electrostatic problems. FinFET managed to survive two more process nodes through "patching".

After entering the 3nm era, Samsung was the first to apply GAAFET technology, while TSMC was relatively conservative and planned to apply it in the 2nm process.

As for the next - generation three - dimensional transistor structure, the Complementary FET (CFET) proposed by IMEC in 2018 is considered a strong competitor.

Why is CFET needed?

As for why CFET is needed, please look at the following pictures.

With the continuous miniaturization of CMOS technology, its scaling logic has changed from simply relying on reducing device spacing (such as gate spacing and metal spacing) to a composite model of "spacing miniaturization + track optimization". Under this new logic, in order to adapt to the layout constraints brought by the increase in track density and balance performance and power consumption, reducing the number of fins has become a necessary design choice.

However, as shown in Figure 1, as the number of fins decreases, the overall performance also decreases.

Figure 1. Standard cell scaling

Figure 2 shows that by switching from FinFET to stacked horizontal nanosheets (HNS), performance can be improved/restored through wider nanosheet stacks and vertically stacking multiple nanosheets. Figure 3 shows that, as seen in FinFET, nanosheet scaling will ultimately lead to performance degradation.

Figure 2. Advantages of nanosheets

Figure 3. Nanosheet scaling limitations

As shown in Figure 4, CFET integrates GAA devices of different conductive channel types (N - FET and P - FET) in a high - density three - dimensional monolithic manner in the vertical direction. Compared with FinFET and GAAFET, CFET breaks through the size limitation of the co - planar layout spacing of traditional N/P - FET, can shrink the scale of logic standard cells in integrated circuits to a 4 - T (Track) height, and at the same time reduce the SRAM cell area by more than 40%.

Figure 4. CFET stacking method

As shown in Figure 5, CFET resets the scaling constraints again. Since the nFET and pFET are stacked, the n - p spacing between the devices becomes vertical instead of horizontal, making the diagram wider.

Figure 5. Improved scaling of CFET

Figure 6 compares the relationship between the performance of HNS and CFET and the cell height, highlighting the advantages of CFET.

Figure 6. Performance of HNS and CFET vs. cell height. Monolithic CFET vs. sequential CFET

According to the technological roadmap previously announced by IMEC, with CFET, the chip process technology is expected to evolve to 5 angstroms (0.5nm) in 2032 and reach 2 angstroms (0.2nm) in 2036. TSMC, Samsung, Intel, etc. have all conducted pre - research and development on CFET in the laboratory.

Now, FlipFET has caused such a large - scale reaction, partly because of its technological advantages, which are even better than those of CFET.

FlipFET, better than CFET

At VLSI 2024 held in June last year, the research team led by Researcher Wu Heng and Academician Huang Ru from Peking University first proposed the FlipFET technology.

At VLSI 2025 this year, Academician Huang Ru's team announced a new - generation three - dimensional transistor structure, the "Flip Stacked Transistor (Flip FET, FFET)", which for the first time achieved the three - dimensional vertical integration of 8 - layer transistors. The logic density per unit area is 3.2 times higher than that of traditional FinFET, and the power consumption is reduced by 58%. This breakthrough result is regarded by the industry as one of the most promising solutions to continue Moore's Law.

There are fundamental differences between FlipFET and CFET technologies.

One of the biggest highlights of FFET technology lies in its unique design of "double - sided active area + flip + back - to - back self - alignment".

CFET (Complementary Field - Effect Transistor) vertically stacks n - type and p - type transistors on the same wafer and shares the same gate to achieve complementary functions. Although this design can significantly reduce the area, it requires precise alignment of multiple layers of materials on the same wafer, resulting in extremely high manufacturing complexity.

Different from CFET, which relies on a complex front - side wafer stacking process, FFET first manufactures n - type transistors (such as FinFET NMOS) on the front side of the wafer, and then bonds another wafer, flips and thins it, and manufactures p - type transistors (such as FinFET PMOS) on the back side. This structure does not require vertical stacking but achieves spatial separation of n/p devices through physical flipping, fundamentally avoiding the multi - layer alignment problem of CFET.

So, what "chronic problems" faced by CFET has FlipFET solved?

First, the vertical stacking of CFET tends to increase the leakage current path, while the double - sided layout of FlipFET naturally isolates the drains of n/p devices.

Second, the vertical stacking of CFET requires extremely high inter - layer alignment accuracy, and any deviation will cause a sharp increase in resistance. FlipFET controls the key alignment error within an acceptable range through self - aligned active areas and back - side lithography correction technology.

Third, the high - temperature process of CFET limits the choice of metal interconnection materials, while the low - temperature process of FlipFET allows the retention of the mature copper interconnection technology.

Fourth, the fixed stacking structure of CFET is difficult to adapt to different application scenarios, while FlipFET supports "progressive innovation". It is not only suitable for the stacking of Fin structures but also for the next - generation GAA nanosheets, with strong expandability.

The high attention paid to FlipFET technology means that in the field of semiconductor technology, an era is coming when an integrated circuit can be formed not only on the front side but also on the back side of a wafer.

Coincidentally, in the "Paper 2.5, TSMC’s Fully Functional Monolithic CFET Inverter at 48nm Gate Pitch" of the IEDM2024 Press Kit, TSMC also almost simultaneously introduced the layout concept of double - sided power supply and double - sided signal interconnection in its latest CFET progress and experimentally demonstrated the feasibility of wafer bonding and flipping (Bonding + Flipping) technology, which also proves the feasibility of the extreme wafer thinning and double - sided lithography technology involved in FlipFET technology.

However, from a technical perspective, there are fundamental differences between the two. The existing method of front - side CFET plus back - side interconnection still follows the traditional three - dimensional integration method of wafer bonding, while FFET tends to equivalently utilize the double - sided integration space of the wafer, thereby expanding the applicable scope of device and interconnection integration layout. Theoretically, it has the same technological iteration ability as the planar integration method, equivalent to the three - dimensional version of the scaling law.

Although the research team has demonstrated FlipFET on silicon wafers, they have not stopped there. They have demonstrated and simulated further innovations in the FlipFET design, such as FlipFET with self - aligned gates, FlipFET using forksheets and embedding power rails in isolation walls, and even applying the FlipFET concept to monolithic CFET with high - aspect - ratio vias to achieve a 4 - stacked transistor design.

When the technical details of FlipFET were made public, it not only represented the debut of a technological achievement - it also meant that China had broken the long - term "following" situation in the field of advanced logic devices. From now on, there is a clearer Chinese voice in the global semiconductor research discourse system. This has also attracted high attention from giants such as TSMC and Intel. The R & D director of TSMC pointed out that this technology "redefines the technological boundaries of three - dimensional integration".

Chips of 1nm and below are on the way

FlipFET and CFET technologies will be used in the more advanced angstrom - scale process technologies in the future. Leaving aside 0.5nm, how long will it take for the nearest 1nm process to arrive?

Previous data showed that TSMC plans to reach the A14 node in 2027 and the A10 node, that is, 1nm process chips, in 2030. By then, the number of transistors in chips using TSMC's 3D packaging technology will exceed 1 trillion, and the number of transistors in chips using traditional packaging technology will exceed 200 billion.

In contrast, the GH100 using the 4nm process and traditional chip packaging path only has 80 billion transistors.

In February this year, market news said that TSMC is planning to build a wafer factory with the most advanced 1nm process node technology production line in Tainan, Taiwan, China. It is reported that this newly built Fab 25 will focus on the production of 12 - inch wafers, and the factory is large enough to accommodate 6 production lines. TSMC has submitted relevant plans to the Southern Taiwan Science Park Administration and revealed the preliminary production line configuration. It is expected that the P1 to P3 production lines of Fab 25 will be equipped with 1.4nm process technology, while the P4 to P6 production lines will be set with the more advanced 1nm process technology.

However, the CFET process should not be used in TSMC's 1nm process. After all, TSMC has just started using GAA technology in the 2nm process.

Intel is also ambitious. It plans to start mass - producing processors based on the 18A process technology in 2025. If 18A can pass the verification tests of design manufacturers such as NVIDIA and Broadcom, Intel will greatly enhance its market competitiveness. Intel's official website shows that the samples of the first - batch products based on the Intel 18A process node - the AI PC client processor Panther Lake and the server processor Clearwater Forest - have left the factory, powered on, and successfully started the operating system.

Intel's 18A process uses RibbonFET gate - all