Who can take over from CoWoS?

In the era of computing power, with the rapid development of NVIDIA's GPUs and the wave of AI chips, CoWoS packaging technology has rapidly emerged with its unique advantages, once becoming the focus of the industry. The market demand has been so strong that it is in short supply.

However, as the application of technology deepens and the industry continues to develop, chip integration is evolving towards system - level innovation with larger areas, higher integration, and shorter interconnection lengths. CoWoS packaging technology has gradually revealed a series of shortcomings and challenges that cannot be ignored: the complexity of its process not only drives up production costs but also brings many problems in yield control and testing. At the same time, it also faces severe tests in electrical characteristics such as interconnection performance and power integrity. Coupled with TSMC's long - standing production capacity bottleneck, these problems are intertwined and have become a significant obstacle restricting the industry's development.

Therefore, the industry is currently turning its attention to new packaging technology fields and actively exploring solutions that can effectively replace CoWoS.

After CoWoS, the Iteration and Competition of Packaging Technologies

CoPoS, Transforming Circles into Squares

Currently, the CoWoS technology is mainly mastered by TSMC. In the short - term technological evolution path, TSMC is promoting the upgrade of CoWoS from the existing CoWoS - S/CoWoS - R versions to the more promising CoWoS - L technology. Compared with its predecessors, CoWoS - L has achieved significant optimization in core indicators such as flexibility and economy.

However, as the size of AI GPU chips increases and the number of HBM stacks grows, CoWoS has encountered a bottleneck - the size of the photolithography mask limits the maximum packaging area of a single module.

To address this challenge, the industry generally believes that CoPoS technology will be the future evolution direction of CoWoS. TSMC has also clearly stated that it positions CoPoS as the next - generation successor to CoWoS and plans to gradually replace CoWoS - L through technological iteration in the future.

As is well - known, CoWoS (Chip - on - Wafer - on - Substrate) belongs to wafer - level packaging. It stacks chips and then packages them on a substrate, ultimately forming 2.5D and 3D shapes, which can reduce chip space and also lower power consumption and costs. CoPoS (Chip - on - Panel - on - Substrate) can be regarded as a panel - based solution for CoWoS.

From a technical architecture perspective, CoPoS is in the same vein as CoWoS. The core difference is that the silicon interposer in CoWoS is replaced with a panel - sized substrate (i.e., the panel - level redistribution layer). This key upgrade enables it to break through the existing technological bottlenecks, achieving a larger packaging size, better area utilization, and greater production flexibility and scalability.

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The core concept of CoPoS is to "transform circles into squares" - replacing wafer - level packaging with a large rectangular panel substrate to reduce incomplete chips that usually appear at the edges of circular wafers.

This design change promotes the integration of more semiconductors in a single package, thereby improving overall computing performance, achieving higher substrate utilization, greater packaging density, improved yield efficiency, reduced edge waste, and lower unit - area costs. For example, CoPoS uses panel - level packaging specifications such as 600mm×600mm, 700mm×700mm, or 310mm×310mm, providing more packaging space, higher I/O integration, and improved production efficiency, making it a natural evolution of the CoWoS platform.

In fact, CoPoS is not simply replacing the silicon interposer with a panel to achieve the "transformation from circle to square", but an all - around innovation involving materials, processes, and equipment.

To support this structural change, the redistribution layer (RDL) process must be significantly enhanced to meet a wide range of packaging requirements such as multi - layer metal stacking, high I/O density, and multi - chip integration.

Meanwhile, as the packaging area and power density increase, TSMC has also introduced advanced materials and technologies - such as glass substrates and through - glass vias (TGV). These materials offer excellent flatness, thermal stability, and vertical interconnection capabilities, thereby improving thermal performance and interconnection flexibility.

In fact, glass substrates are also very important for the CoPoS process.

With characteristics such as low thermal expansion coefficient, high mechanical strength, high temperature resistance, and high wiring density, glass substrates are regarded as the next - generation substrate solution for semiconductors. As early as September 2023, Intel publicly announced its efforts in glass core substrates, believing that this technology will redefine the boundaries of chip packaging, provide breakthrough solutions for data centers, artificial intelligence, and graphics processing, and promote the further development of Moore's Law. After Intel took the lead in presenting glass substrate technology, the industry has shown great interest in this topic and is promoting industry chain manufacturers to increase investment in this technology. It is expected that relatively clear progress and breakthroughs will be seen within a few years.

In terms of market progress, both CoWoS and CoPoS are advanced packaging technologies led by TSMC. Currently, TSMC has launched a CoPoS pilot line. It is reported that TSMC will set up the first CoPoS packaging technology experimental line at its subsidiary Caiyu in 2026. Meanwhile, the CoPoS mass - production factory for large - scale production has been confirmed to be located in Chiayi AP7, with the goal of achieving large - scale mass production of this technology between the end of 2028 and 2029. NVIDIA will be the first customer.

Looking to the future, both CoWoS and CoPoS focus on the collaborative optimization of HBM and processors. As the demand for computing power in AI surges, CoWoS - R/L and CoPoS will develop in parallel - the former meets scenarios where performance is prioritized, and the latter promotes large - scale mass production, jointly supporting the 3D packaging ecosystem.

Industry Giants Flocking to the FOPLP Track

Recently, there have been frequent reports in the industry about FOPLP advanced packaging.

• SpaceX, owned by Elon Musk, intends to enter the panel - level fan - out packaging (FOPLP) field and plans to build its own chip packaging factory in Texas. Its substrate size is 700mm×700mm, the largest in the industry.
• ASE Technology Holding has invested $200 million in purchasing equipment and established a production line at its Kaohsiung factory. It plans to start trial production of FOPLP by the end of this year.
• NVIDIA planned to adopt FOPLP technology for its GB200 AI server chips last year, aiming to solve the problem of tight CoWoS packaging production capacity at TSMC.

Industry insiders point out that in the field of AI chip packaging, FOPLP is expected to become one of the main alternative technologies to CoWoS.

To understand panel - level fan - out packaging (FOPLP), one must first trace its technological origin - fan - out wafer - level packaging (Fan - Out Wafer Level Packaging, FOWLP). This technology was proposed by Infineon in 2004 and achieved mass production in 2009. However, it was only applied to mobile phone baseband chips in the early stage and soon faced market saturation. It was not until 2016 that TSMC developed the Integrated Fan - Out (InFO) packaging based on FOWLP and successfully applied it to the A10 processor of Apple's iPhone 7 series, which then promoted the semiconductor industry to accelerate the layout of FOWLP technology.

As an extended technology of FOWLP, FOPLP inherits the core advantages of the former, such as high I/O density and thin - type design. The key difference between the two lies only in the carrier form - replacing the "wafer" with a "panel", and this one - word difference directly brings about a significant improvement in size and utilization.

Specifically, FOPLP is a technological integration of fan - out packaging and panel - level packaging, combining the core advantages of both types of technologies:

• Relying on the characteristics of fan - out packaging, the wiring of its redistribution layer (RDL) can break through the chip size limit, support more external I/O interfaces, achieve high - density connection and thin - type packaging, and meet the requirements for product thinness while reducing costs.
• Benefiting from the advantages of panel - level packaging, using metal, glass, or polymer as the carrier board can achieve a larger packaging size and higher production flexibility. Its area utilization rate exceeds 95%, significantly higher than the 85% of traditional wafer - level packaging, and it has the characteristics of strong mass - production ability, low cost, and short cycle. Compared with circular wafers, the cost of panel - type packaging can be reduced by more than 20%.

With the development of artificial intelligence technology, the demand for large - size chip packaging has become increasingly prominent, and FOPLP has therefore attracted wide attention from the industry.

As the two mainstream technologies of fan - out packaging, FOWLP and FOPLP have completely different development paths: FOWLP focuses on direct wafer packaging, emphasizing achieving a smaller volume and higher integration, and is suitable for large - scale chips such as CPUs, GPUs, and FPGAs. FOPLP meets a wider range of scenario requirements through panel - level packaging, including high - power, high - current power semiconductors, and does not rely on the most advanced processes and equipment, with a lower technological implementation threshold.

It is worth noting that the FOPLP packaging technology is closely related to panel processes, but there are differences in process strategies and performance applicability compared with the aforementioned CoPoS:

Statistics from market analysis institution Yole show that the market size of FOPLP was approximately $41 million in 2022. It is expected to have a compound annual growth rate of 32.5% in the next five years and reach $221 million by 2028. In the future, with more manufacturers' layout and promotion, as well as better cost - effectiveness brought by higher yields, FOPLP is expected to achieve growth in the next few years.

Facing the huge market potential, the industry currently regards panel - level packaging as the key battlefield for the next - generation advanced packaging technology, attracting major giants to actively develop FOPLP packaging technology.

●Industry Giants Flocking to the FOPLP Track

ASE Technology Holding has been laying out in the FOPLP field for a long time. It started relevant R & D work ten years ago. Initially, it used the 300mm×300mm specification for technology verification. After the trial production results met the standards, it increased the size to 600mm×600mm and placed an order for equipment procurement last year.

In February this year, Wu Tianyu, the COO of ASE Technology Holding, announced that it will invest $200 million in building an FOPLP mass - production line at its Kaohsiung factory in Taiwan, China, covering key process modules such as Chip First, RDL First, and through - glass vias (TGV). The goal is to expand the existing FOWLP technology capabilities to the fields of larger - area packaging and heterogeneous integration to meet the growing market demand in AI, high - performance computing, automotive electronics, and storage modules.

According to the plan, the relevant equipment will arrive at the factory in the second quarter, and trial mass - production will start in the third quarter. The 600mm×600mm specification machine is expected to complete trial production by the end of this year. If the progress is smooth, it can be officially mass - produced and shipped after passing the customer verification next year. If the packaging yield of the 600mm×600mm specification can meet the expectations, it is expected to attract more customers and products, promoting this specification to become the industry mainstream.

As an important participant in the advanced packaging field, Samsung also shows great interest in the FOPLP process. It is reported that Samsung acquired the panel - level packaging (PLP) business from Samsung Electro - Mechanics for 785 billion won as early as 2019. This strategic layout laid the foundation for its subsequent development in this field.

At the general meeting of shareholders in March last year, Kyung Kye - hyun, the then head of Samsung Electronics' semiconductor division, pointed out that AI semiconductor chips usually require large - size packaging of 600mm×600mm or even 800mm×800mm, and such demands need technologies such as PLP to support. At that time, Samsung was actively promoting relevant technology R & D and carrying out customer cooperation. Currently, Samsung has started deploying FOPLP technology for advanced processes. Its Exynos W920 processor used in wearable devices adopts the 5nm EUV process and the FOPLP packaging solution, realizing the implementation of the technology.

TSMC is also an active promoter of FOPLP technology. Currently, it is vigorously promoting the R & D of the FOPLP process. It has not only established a dedicated R & D team but also planned a dedicated production line, but the overall progress is still in its infancy. In August 2024, TSMC announced that it plans to spend NT$17.14 billion to purchase a factory building and ancillary facilities in South Taiwan Science Park from Innolux. According to the news at the end of last year, TSMC will initially choose a smaller 300×300mm panel to enter the FOPLP field and is expected to complete the construction of a small - scale trial - production line as soon as 2026.

Reports point out that TSMC initially preferred to use a 515×510mm rectangular substrate. Compared with the traditional 12 - inch circular wafer, the available area of this specification substrate can be tripled. Later, it successively tested different sizes such as 600×600mm and 300×300mm, and finally decided to start with the 300×300mm specification to gain experience. It will expand to larger sizes after the technology matures. This decision is mainly based on two considerations: one is the control of equipment holding costs, and the other is the limit of the maximum photomask size supported by the existing technology.

It is worth noting that the current FOPLP technology is still in the development stage, and the supporting equipment and processes are not fully mature. There is still room for improvement in