RISC-V: Marching Towards High-Performance Computing

"Looking ahead to the future development of China's CPUs, the RISC-V instruction set architecture, which combines the features of autonomy, controllability, and prosperity, has almost become a must-have option." At the 2025 RISC-V Global Summit held recently at the Zhangjiang Science Hall in Shanghai, Dai Weimin, the founder, chairman, and president of VeriSilicon Holdings Co., Ltd., and the chairman of the Shanghai Open Processor Industry Innovation Center, made the above remarks when evaluating the significance of developing RISC-V products.

Against the backdrop of AI applications and algorithm innovation, RISC-V, as an open-source instruction set architecture, has seen development opportunities in recent years. In terms of the most-watched application implementation progress, RISC-V is not only continuously breaking through commercialization difficulties, but its application scenarios are also gradually expanding from large-scale applications in the edge devices such as AIoT to the more strategically important high-performance computing field.

At this summit, many semiconductor industry practitioners believe that the open and extensible features of the RISC-V instruction set make it more suitable for AI computing requirements in the future.

Marching towards High-Performance Computing: RISC-V Has Initial Ecological Foundation

According to the statistics and forecasts of the SHD Group report, the market penetration rate of RISC-V-based SoC chips will increase from 5.9% to 25.7% from 2024 to 2031. By 2031, the shipment volume of RISC-V chips will exceed 20 billion, and it is expected to occupy a significant share in the following six major markets: consumer electronics (39%), computers (33%), automotive (31%), data centers (28%), industrial (27%), and network communication (26%). The total shipment volume will exceed 20 billion.

It is reported that RISC-V entered the initial stage of commercialization in China in 2019, and AIoT chips became the initial mass-production breakthrough for RISC-V.

"The features of the RISC-V reduced instruction set, the scalable architecture, and high configurability make it naturally suitable for embedded and control chips with limited resources." Hu Zhenbo, the founder of Nuclei System Technology Co., Ltd., said in his speech at the 2025 RISC-V Global Summit.

Among A-share companies, manufacturers such as GigaDevice Semiconductor Inc., ZKLANX Co., Ltd., and Espressif Systems (Shanghai) Co., Ltd. all released their first RISC-V-based chip products between 2019 and 2020. Companies such as VeriSilicon Holdings Co., Ltd., Beijing JZ56 Technology Co., Ltd., Allwinner Technology Co., Ltd., and GUOXIN TECHNOLOGY CO., LTD. are currently promoting mass-production projects of IP or chips based on the RISC-V instruction set, but their applications in scenarios such as AI still need to achieve large-scale breakthroughs.

Among startups, domestic RISC-V chip companies include Zhongke Wuqi Technology Co., Ltd., Shiqing Technology Co., Ltd., Zhongke Wuxin Technology Co., Ltd., StarFive Technology Co., Ltd., RiseKernel Technology Co., Ltd., and Nuclei System Technology Co., Ltd., which all focus on IP or AIoT products and were mostly established around 2019.

Hu Zhenbo believes that the current expansion of RISC-V to high-performance applications has initially established an ecological foundation.

It is reported that since 2021, the RISC-V community has begun to focus on general-purpose processors with medium to high performance and high energy efficiency, gradually benchmarking against ARM Cortex-A53/A55. RISC-V cores with MMU and support for running the Linux system have become the key focus for manufacturers, aiming to enter the main control scenarios such as industrial control, human-computer interaction, and intelligent gateways.

Around 2022, many manufacturers successively launched benchmark-level IPs, promoting RISC-V to multi-task and high-complexity systems. As the software stack is gradually improved and the support for toolchains, RTOS/Linux is enhanced, RISC-V is continuously moving from "embedded control" to "general computing core".

In 2024, as the AI inference computing power is moved down to edge and terminal devices, the role of RISC-V as the control and scheduling core in AI chips has been further strengthened.

"By 2025, RISC-V will achieve substantial breakthroughs in the three core fields of AI computing, automotive electronics, and high-performance general processing, and RISC-V CPU IP will also extend to scenarios with higher performance." In Hu Zhenbo's view, this is due to the further maturity at the software and hardware levels.

At the hardware level, the stability and maturity of high-performance out-of-order triple-issue, quadruple-issue, and sextuple-issue RISC-V CPU IP hardware have reached a certain level.

At the software ecosystem level, the architecture specification system represented by the RVA23 Profile marks that the standardization process of RISC-V on the 64-bit general computing platform has entered a new stage. Especially, its ability to support operating systems, virtualization, and application layer operating environments has been continuously improved, laying an architectural foundation for running systems such as Linux and Android.

According to statistics from third-party institutions, the total market size of RISC-V-based SoCs was approximately $6.1 billion in 2023 and is expected to reach $92 billion in 2030. Among them, AI accelerator chips will become the largest part of all RISC-V SOCs, with the total market size expected to reach $42 billion in 2030, with a CAGR of up to 49.2%, which is an important part of the growth expectation for RISC-V.

Multi-Core Heterogeneous: RISC-V May Bring a Leap in Computing Efficiency

The most advantageous function of RISC-V in high-performance computing scenarios such as AI is that it can act as a control core or exert general parallel computing capabilities to improve computing efficiency.

Building high-performance computing chips based on RISC-V has become a consensus among different computing power manufacturers.

Hu Zhenbo of Nuclei System Technology Co., Ltd. said that the demand for highly parallel Vector Cores in AI chips is almost a necessity, and at the same time, the AI chip architecture has extremely high requirements for customization and power consumption control. The scalability, openness, and low power consumption features of RISC-V are naturally compatible with AI scenarios.

"More and more AI chip manufacturers are choosing RISC-V to replace traditional ARM M-class/A-class cores, forming a structural paradigm of multi-core heterogeneous + programmable control. The Vector Processor Unit (VPU) based on RISC-V can well assist accelerators such as GPUs and NPUs to provide more general performance." Hu Zhenbo said.

Taking NVIDIA as an example, the company replaced its original Falcon processor with a control unit based on the RISC-V instruction set architecture as early as 2016 and used it as the core controller for its GPUs.

At the 2025 RISC-V Global Summit, Frans Sijstermans, the vice president of hardware engineering at NVIDIA, revealed that NVIDIA is actively promoting the transplantation of CUDA to the RISC-V architecture. Previously, CUDA was only deployed on x86 and ARM architectures.

According to the NVIDIA NVLink Fusion technology blueprint presented by Frans Sijstermans, it will integrate RISC-V CPUs, GPUs, network chips, and NVLink interconnection technology to build a complete data center-level architecture. Among them, NVLink Fusion not only supports replacing traditional x86/Arm architectures with RISC-V CPUs but also allows seamless integration of accelerators (such as Blackwell, Grace CPU) with custom chips through a flexible modular design.

The transplantation of NVIDIA's CUDA toolchain to RISC-V means that developers can freely choose the data center CPU architecture, which will promote the widespread application of RISC-V in the high-performance computing field at the ecological level.

Tenstorrent, a leading chip company in the RISC-V field, designed its Blackhole AI chip as a computing matrix with 16 Big RISC-V cores and 752 Baby RISC-V cores. Among them, 16 large cores are used for general computing, and 752 small cores are used for accelerated computing. It is reported that the performance of this new product can reach up to 745 TOPS, and its overall AI performance and scalability are better than NVIDIA's A100 product.

A relevant person in charge of SOPHGO TECHNOLOGY CO., LTD., a domestic custom computing power provider, said at the 2025 RISC-V Global Summit that the company released the industry's first 64-core high-performance RISC-V CPU SG2042 in 2023, realizing the commercialization of high-performance processors based on the RISC-V architecture. It also adapted its self-developed TPU, accelerator cards, or other products to the RISC-V high-performance server base to create a fusion server, targeting specific application scenarios and achieving a closed-loop. With the second-generation high-performance RISC-V processor SG2044, SOPHGO TECHNOLOGY CO., LTD. moved the heterogeneous integration technology such as TPU from outside the chip to inside the chip, further improving the product performance.

In addition, technological breakthroughs in the RISC-V field, such as the Xiangshan high-performance processor core IP and the Xuantie C930 server chip, have verified the feasibility of RISC-V in the high-performance computing field.

It is understood that the Xuantie team released the large-bitwidth Vector engine Xuantie TITAN at the 2025 RISC-V Global Summit, which supports a scalable vector length configuration of 512 - 4096 bits and can achieve instruction-level parallel acceleration. Xuantie also newly designed the tensor computing power engine TPE (Tensor Processing Engine), which is a native architecture more suitable for AI, with the GEMM computing power execution rate increased to 96.8%, and it can be adapted to real-time training scenarios for large models.

Challenges Remain for the Explosion of RISC-V Applications

"The application footprint of RISC-V has covered many key scenarios in the embedded field, but the overall foundation is still not solid enough, and the development structure shows the characteristics of 'sufficient in specialization but insufficient in generalization'." According to Hu Zhenbo, in specialized scenarios, RISC-V products have been widely deployed in closed and customized chips such as communication, Wi-Fi, and SSD, mostly in control and non-user-perceptible scenarios, which are easy to implement, have a short cycle, and high customization, but their implementation in general scenarios is still weak.

"Improving the software ecosystem is a necessary condition for the productization of RISC-V high-performance servers." A relevant person in charge of SOPHGO TECHNOLOGY CO., LTD. said at the 2025 RISC-V Global Summit that the challenges in building the software ecosystem for RISC-V productization include: at the ecological level, there is insufficient support for debugging and Trace tools, domestic CPU IP manufacturers have poor support for RISC-V debugging specifications, and foreign proprietary debugger manufacturers have limited support for domestic IPs; at the operating system level, the process of driving the mainline for SoC manufacturers is slow, resulting in the need for distribution versions to maintain their own kernels, increasing the adaptation cost; at the performance bottleneck level, the performance of CPU cores still cannot reach the level of mainstream X86 and ARM servers, and the optimization ability of compilers needs to be improved.

Bao Yungang, the secretary-general of the China Open Instruction Ecosystem (RISC-V) Alliance and the chief scientist of the Beijing Open Source Chip Institute, said in his keynote speech at the 2025 RISC-V Global Summit that there is an urgent need to establish industry confidence through benchmark cases, and there is a shortage of talents at all levels, including chip design, verification, solutions, and technical support.

Meng Jianyi, the CEO of ZHH Computing, also said that the industry needs to launch more products with good generality. Benchmark products can drive the explosion of the ecosystem, and only after the ecosystem is well-established can better innovation be achieved, thus building a closed-loop for product mass production. "For this reason, we may need to view the development of RISC-V over a 10-year cycle."

This article is from the WeChat official account "Sci-Tech Innovation Board Daily", author: Guo Hui, published by 36Kr with authorization.