Chips, the latest roadmap

Recently, YouTube blogger @TechTechPotato shared and interpreted in - depth the semiconductor process roadmap released by IMEC (Interuniversity Microelectronics Centre) in a video.

As is well - known, as the core hub of global semiconductor process R & D, IMEC, relying on its top - notch research teams, advanced infrastructure, and a unique model of collaborative innovation among industry, academia, and research, has long led the development of industry technology. Its authority and foresight in the semiconductor field are highly recognized by the industry.

Therefore, IMEC's prediction of the future semiconductor roadmap not only demonstrates its profound insight into industry trends but also provides a highly valuable reference direction for global semiconductor enterprises and research institutions. Next, this article will focus on this latest roadmap and conduct an in - depth analysis of its predictions and outlooks for the future development of semiconductor technology.

Interpretation of the IMEC Roadmap

IMEC has recently updated its roadmap up to 2039. This roadmap predicts the evolution process of process node technology in the next 14 years, covering emerging new technologies and the evolution of process nodes.

IMEC's predicted roadmap up to 2039 (Source: YouTube blogger @TechTechPotato)

In it, IMEC elaborates in detail on how to predict the development trends and evolution processes of technologies such as chip process nodes, transistor architectures, chip interconnection architectures, back - side power supply technology, EUV lithography machines, and 2D materials, as well as the difficulties and challenges when these technologies move from the laboratory to industrial implementation.

Next, let's delve into the secrets of the future development of the semiconductor industry hidden behind this roadmap.

First, understand the naming method of chip process nodes

At present, 7 - nanometer, 5 - nanometer, and 3 - nanometer chips have become the mainstream technologies for advanced processors. However, few people know that these numbers have long deviated from their original physical size meanings and have evolved into a kind of conventional naming symbols.

Looking back at the development history of chip processes, in the early era of planar transistors, the numbers of process nodes accurately corresponded to physical sizes such as the gate pitch and line - to - line pitch of transistors. Names like 90 - nanometer and 65 - nanometer directly reflected the minimum feature sizes in chip manufacturing. However, as semiconductor technology approached the physical limit, when FinFET (Fin Field - Effect Transistor) replaced planar transistors and pushed chips from a two - dimensional structure to a three - dimensional architecture, this naming logic began to collapse.

Source: YouTube blogger @TechTechPotato

Three - dimensional transistors significantly improve transistor performance through a vertical stacking structure and no longer rely solely on size reduction to achieve performance leaps. Under the new technological path, the improvement of chip performance stems more from architectural innovation and density optimization rather than the traditional physical size shrinkage.

Source: YouTube blogger @TechTechPotato

Today, the naming of chip process nodes is essentially a continuation of the concept of "equivalent planar transistors" and a tacit understanding formed by the semiconductor industry based on historical naming habits and market perception. Although "3 - nanometer" and "5 - nanometer" no longer correspond to the actual gate pitch or minimum feature size, these numbers still carry the industry's evaluation criteria for technological advancement and have become important identifiers for measuring the generational evolution of chip manufacturing processes.

The End of the FinFET Era

The above roadmap is IMEC's naming method, which is not entirely consistent with the naming of process nodes by TSMC, Samsung, or Intel. However, according to IMEC's updated roadmap, from 2018 to 2025, the evolution of N7, N5, N3, and N2 process nodes has taken place.

Notably, with the evolution from N3 to N2, the transistor architecture has gradually evolved from FinFET (Fin Field - Effect Transistor) to NanoSheet transistor architecture.

Looking back at the development history of semiconductor process technology, planar transistors dominated for a long time in the past.

With the development trend of semiconductors, the idea of packing more transistors into the same area has gradually gained attention, leading to the concept of overall size miniaturization, with the gate size being the key focus for miniaturization.

However, planar transistors are limited by their physical structure. They can only control the on - and - off of the current on one side of the gate, and the gate width cannot be infinitely narrowed. When the width approaches 20nm, the gate's control ability over the current will decline sharply. The industry calls this the "so - called short - channel effect caused by the shortening of the channel length," resulting in a serious current leakage phenomenon, which ultimately makes the heat generation and power consumption of the chip out of control.

At this point, the traditional planar MOSFET structure has reached its end. To continue Moore's Law, Professor Hu Zhengming proposed the FinFET architecture around 2000.

Intel was the first to launch a commercial FinFET process technology in 2011, applying the FinFET technology to its 22nm process technology, significantly improving performance and reducing power consumption. Later, global manufacturers such as TSMC and Samsung followed suit. The adoption of FinFET technology has achieved great success, making FinFET shine. Starting from 16/14nm, FinFET has become the mainstream choice for semiconductor devices and has successfully promoted the development of several generations of semiconductor processes from 22nm to 5nm and even 3nm.

The most significant feature of FinFET is that it changes the transistor structure from planar to three - dimensional and reforms the shape of the gate. The gate is designed into a fork - shaped 3D architecture similar to a fish fin, controlling the on - and - off of the current on both sides of the circuit, greatly increasing the contact area between the source and the gate, reducing the gate width while lowering the leakage rate, and greatly increasing the space utilization rate of the transistor.

Since the commercialization of FinFET process technology in 2011, its architecture has been continuously improved to enhance performance and reduce the area. After the 5nm node, although EUV lithography technology has been used, it has become increasingly difficult to reduce the chip size based on the FinFET structure.

In the process of advancing to more advanced process nodes, the limitations of the FinFET chip process node are gradually emerging. When the process approaches smaller sizes, especially when exploring nodes below 2nm, the quantum tunneling effect poses a huge challenge. With an extremely thin gate dielectric layer, the quantum characteristics of electrons become more prominent, the tunneling current increases significantly, resulting in a sharp rise in leakage current, a significant increase in power consumption, and serious impacts on transistor performance and reliability.

The traditional FinFET structure has difficulty effectively addressing this issue, prompting the industry to urgently seek new solutions.

The NanoSheet Era: New Upgrades in Materials, Equipment, and Technology!

Against this background, the NanoSheet transistor architecture has emerged.

IMEC's roadmap also indicates that with the arrival of the N2 process node, the NanoSheet architecture era will begin.

Compared with FinFET, NanoSheet adopts a Gate - All - Around (GAA) structure, where the conductive channel is fully surrounded by high - dielectric - constant materials or metal gates. Even when the channel is shortened, it can greatly enhance the gate's control ability over the channel and effectively suppress the leakage current problem caused by the quantum tunneling effect. Moreover, NanoSheet can provide a higher driving current than FinFET in the same size by vertically stacking multiple conductive channels, providing a new direction for chip performance improvement and process miniaturization and is expected to lead the semiconductor industry to break through the current dilemma and continue to promote chip technology towards higher performance and lower power consumption.

In fact, when Samsung and Intel, two major wafer foundry giants, switched to the GAA process a few years ago, it indicated that FinFET had reached the end in more advanced nodes and would gradually be replaced by the GAA architecture.

TSMC also disclosed its A14 (1.4 - nanometer level) manufacturing technology at the 2025 North American Technology Symposium, promising that this technology will be significantly superior to its N2 (2 - nanometer) process in terms of performance, power consumption, and transistor density.

TSMC said that the new node will rely on the second - generation Gate - All - Around (GAA) NanoSheet transistors and provide further flexibility through NanoFlex Pro technology. It is expected that A14 will enter mass production in 2028 but will not support back - side power supply. The A14 version supporting back - side power supply is planned to be launched in 2029.

It can be seen that transferring from FinFET to NanoSheet Gate - All - Around technology is another way to improve transistor performance by surrounding the gate.

The Debut of High NA EUV Lithography Technology

Meanwhile, from IMEC's roadmap, it can also be seen that during the evolution from N2 to A14, the lithography machines required for these advanced - process chips are also transitioning from 0.33NA EUV to 0.55NA EUV.

In the evolution history of semiconductor processes, the implementation of the first - generation FinFET transistor technology preceded the popularization of EUV lithography technology. When the process nodes were iterated from N5 to N3 and N2, the standard EUV (0.33 NA EUV) technology had become the core support for the FinFET architecture. Although the cost of a single EUV lithography machine is as high as 150 - 200 million US dollars, its ability to achieve nanoscale pattern transfer through extreme ultraviolet lithography is still the key to improving chip density and performance in current advanced processes.

As the process transitions to the NanoSheet architecture, the semiconductor industry is facing another innovation in lithography technology - High NA EUV (0.55 NA) technology will gradually replace the standard EUV.

Here, NA (Numerical Aperture) essentially determines the resolution limit of the lithography system: The 0.33 NA technology of standard EUV achieves 3 - nanometer - level feature sizes through a 13.5nm extreme ultraviolet wavelength in combination with multiple - exposure processes; while High NA EUV increases the numerical aperture to 0.55 and, combined with a more complex optical system design, can directly achieve single - exposure fine pattern formation for nodes below 2nm, fundamentally breaking through the resolution bottleneck of standard EUV in the NanoSheet era.

IMEC's roadmap shows that when the process node evolves to around A14 (equivalent to a planar size of about 1.4nm), the optical limit of standard EUV will be difficult to support the atomic - level precision pattern transfer required by the NanoSheet architecture.

The debut of High NA EUV at this time has dual significance: On the one hand, through higher light - collection efficiency and shorter depth - of - focus control, it solves the problems of line - width roughness (LWR) and overlay error faced by standard EUV at extremely small pitches; on the other hand, the three - dimensional structure of the Gate - All - Around (GAA) required by the NanoSheet architecture needs the vertical - dimension precision control provided by high NA EUV to achieve the uniformity and reliability of multi - layer NanoSheet stacking.

From a technical logic perspective, the evolution of EUV lithography technology has always been deeply bound to transistor architecture innovation: In the FinFET era, standard EUV met the patterning requirements of three - dimensional fins through multiple exposures; in the NanoSheet era, High NA EUV will support next - generation process technologies such as atomic - layer deposition and two - dimensional material integration with higher optical resolution, continuously providing the cornerstone for the upgrade of computing power density in cutting - edge fields such as AI chips and quantum computing. This also means that when the A14 node arrives, the semiconductor industry will witness a collaborative revolution in lithography technology and device architecture.

The Appearance of Back - Side Power Supply Technology

In traditional transistor design, data signals and power need to be transmitted to complex transistor arrays through planar lines, and the crosstalk problem between lines has always restricted chip performance.

Therefore, starting from the N2 process node, the semiconductor industry has witnessed a key innovation - back - side power supply technology, which is expected to be continuously deepened in more advanced nodes such as A14 to A10 and become the core solution to break through the performance bottleneck.

The core of back - side power supply technology lies in transferring the traditional power - transmission path on the front side of the transistor to the back side of the chip and reconstructing the power network through a three - dimensional architecture. This change brings two major advantages:

• Reducing Crosstalk and Improving Data Integrity: Separating the power and data lines to the front and back sides of the chip significantly reduces electromagnetic interference between lines, making high - frequency data transmission more stable, especially suitable for scenarios with extremely high requirements for signal integrity, such as AI chips and data - center processors.
• Optimizing the Balance between Power Consumption and Performance: Back - side power supply can directly provide more precise voltage control for the transistor array. In combination with three - dimensional transistor architectures such as FinFET and NanoSheet, it can achieve a performance breakthrough of "low voltage and high drive." For example, in the A10 node, this technology can reduce chip power consumption by 30% while increasing the operation speed by 20%.

However, technological innovation is accompanied by a significant increase in manufacturing complexity. When introducing back - side