CoPoS is coming, the packaging has changed

AI chips are getting increasingly larger, and advanced packaging is also exploring new production methods.

In the past, CoWoS was one of the core technical routes for advanced packaging. However, as the integration scale of GPUs and HBM continues to expand, the limitations of traditional wafer-level packaging in area utilization have gradually emerged, pushing the industry to shift its focus to CoPoS, namely Chip-on-Panel-on-Substrate.

The most intuitive difference between the two solutions is that the processing carrier changes from a circular wafer to a rectangular panel. According to the analysis released by Yong-woon Kang, CEO of Infomarket, on October 22, TSMC is advancing R&D in this direction, while Samsung Electro-Mechanics is also recognized as exploring related technologies.

The opportunities brought by this transformation are not limited to the packaging process itself, but also extend to the equipment and material sectors. Among them, the 40mm-class thermal compression bonder, MSVP precision dicing system, and 120mm-class thermal compression bonder are the three types of equipment that Infomarket pays close attention to. Looking further ahead, with the development of glass core substrates and glass interposers, the demand for related equipment is expected to embrace a new round of growth.

From Wafer to Panel, What Changes Have Occurred in the Packaging Process?

To understand the equipment opportunities brought by CoPoS, we first need to clarify its production workflow.

In the solution introduced by Infomarket, CoPoS adopts an organic redistribution layer (RDL) as the interposer structure. Fine circuits are first fabricated on a temporary glass carrier, then GPU chips and HBM stacks are mounted on the RDL. After molding, carrier stripping and dicing, the independent packaged units are finally connected to the organic packaging substrate.

There is a point that is easy to confuse: **The glass in the current CoPoS solution is mainly used as a temporary carrier, and the final RDL interposer still adopts an organic material structure.** Using glass as a permanent substrate or interposer is another technical route that may be developed in the follow-up stage.

RDL is the core of this process. It is responsible for redistributing the electrical connections between chips. The representative linewidth given in the reference is about 2 microns, which is far smaller than the common linewidth of 10 microns or more for traditional packaging substrates. To fabricate such ultra-fine circuits, the relatively flat surface of the glass carrier is required, and a release layer is set between the glass and the RDL to facilitate subsequent glass stripping.

After the RDL fabrication is completed, the GPU and HBM are mounted side by side on the panel. Subsequently, the molding compound encapsulates the chips and RDL, providing mechanical strength for the originally thin structure that cannot support itself independently. After the glass carrier is removed, the entire panel is diced into individual packaged units, which are finally connected to the packaging substrate.

This workflow seems to only replace circular wafers with rectangular panels, but in fact, every link puts forward new requirements for equipment.

For example, the panel size specified in the reference is gradually expanded from 310×310mm to 515×510mm. The total area of the latter is more than 3.5 times that of a 300mm wafer, and the rectangular panel can reduce the area loss at the edge of the circular wafer when arranging rectangular packages.

As the panel becomes larger, the area that can be covered in a single processing session increases accordingly, but the equipment must simultaneously solve problems such as precision mounting, large-area dicing, and package warpage. This is exactly why CoPoS drives a new round of equipment demand.

Three Types of Equipment That First Embrace New Application Demands

In this process, chip mounting, panel dicing after molding, and the connection between the packaged unit and the substrate are three links worthy of attention.

The first is the 40mm-class TC thermal compression bonder.

After the RDL is fabricated, GPU chips and HBM stacks need to be mounted to the designated positions one by one. The representative dimensions given in the reference are: the GPU chip is about 26×33mm, the HBM stack is about 11×12mm, the micro-bump pitch is about 25 to 40 microns, and the mounting alignment accuracy is about ±1 to 2 microns.

This type of mounting requires the equipment to complete the connection through heating and pressure. The 40mm-class TC bonder is designed to meet the chip mounting requirements at this stage. Since a large number of mounting operations need to be performed on one panel, as the panel output increases, the production line needs to be configured with corresponding bonding capabilities.

After the chip mounting is completed, the packaging structure goes through molding, and then the temporary glass carrier is stripped. Next, the equipment needs to dice the large molded panel into independent packaged units.

This link corresponds to the MSVP system.

MSVP is the abbreviation of Micro SAW & VISION PLACEMENT, which integrates functions such as dicing, cleaning, inspection and placement. According to the reference, the size of the independent packaged unit formed by CoPoS is about 69 to 90mm square, and its area is about 5.5 to 9.5 times the exposure field of view of a single photolithography mask.

Compared with traditional packaging substrates, this type of structure contains thin RDL, molding compound and chips at the same time, which requires more precise control of the processing process during dicing. Therefore, panel-level packaging provides a new application scenario for MSVP equipment.

The third type of equipment is the 120mm-class TC bonder used for connecting the packaged unit and the substrate.

After dicing, each GPU and HBM packaged unit needs to be individually connected to the organic packaging substrate, instead of bonding the entire panel to the substrate at one time. The substrate size given in the reference is about 100 to 120mm, the C4 solder bump pitch is about 100 to 130 microns, and the alignment accuracy is about ±10 microns.

Compared with the previous chip mounting process, the alignment accuracy requirement in this link is relatively loose, and the real difficulty lies in the warpage control during large-area bonding. The packaged unit and the substrate may deform to varying degrees during the heating process, so it is necessary to ensure the uniformity of temperature and pressure in the large area as much as possible.

The 120mm-class TC bonder is developed for this demand. It should be noted that 120mm refers to the upper limit of the bonding area capacity of the equipment, which does not mean that the width of a single packaged unit has reached 120mm at present.

As for hybrid bonding, Infomarket believes that its application scope in this organic RDL panel-level process is relatively limited. The reason is that fine RDL circuits do not mean that the surface naturally meets the flatness required for hybrid bonding, and organic panels cannot be directly regarded as having the same bonding conditions as properly processed wafers. Therefore, hybrid bonding is more suitable for specific interfaces where it is truly needed.

From Temporary Glass Carrier to Permanent Glass Substrate

If CoPoS first changes the production carrier of packaging, the next change worthy of attention is that glass evolves from a temporary carrier to a part of the packaging structure itself.

At present, after the glass in CoPoS completes RDL fabrication, chip mounting and molding, the glass carrier needs to be stripped by laser acting on the release layer. If a glass core substrate is adopted in the follow-up, glass will no longer only be used to support the processing process, but will become part of the final packaging substrate.

The idea of the glass core substrate is to replace the core layer in the traditional organic packaging substrate with glass. According to the reference, the thermal expansion coefficient of glass is about 3 to 9 ppm/K, while that of the organic core layer is about 15 to 17 ppm/K. The lower thermal expansion coefficient and higher flatness are expected to help control the warpage of large-size packages.

Taking one step further is the glass interposer. In this solution, RDL is directly fabricated on the glass, the glass remains in the final structure, and vertical electrical connections are provided through copper-filled Through Glass Vias (TGV). If this architecture is implemented, part of the temporary carrier stripping and related transfer processes are expected to be omitted.

However, the technical challenges faced by glass core substrates and glass interposers are different. The former first needs to solve problems such as materials, processing, warpage and mass production inspection; the latter also needs to achieve fine circuits of about 2 microns on glass and combine with the TGV process, which has higher technical requirements.

Glass itself is relatively fragile, which will also change the design requirements of equipment. Dicing may shift from traditional sawing to controllable separation after laser modification, and the bonding equipment needs to fix the glass while avoiding cracking and damage.

Samsung Electro-Mechanics has established a glass substrate pilot production line and publicly set a mass production target for 2027; LG Innotek has also announced that it will carry out R&D on glass substrates. Infomarket also mentioned that Samsung Electro-Mechanics is exploring the organic RDL interposer solution.

These two routes need to be distinguished: the organic RDL interposer is located under the chip, while the glass core substrate corresponds to the core layer inside the packaging substrate. For manufacturers that already have FC-BGA substrate business, whether to further enter RDL and interposer manufacturing or give priority to developing glass core substrates in the future will be different strategic choices.

HBM and Optical Interconnection Are Also Promoting the Expansion of Packaging Size

The continuous expansion of packaging panels also has another important reason: the integration method of GPU and HBM is changing.

As HBM develops toward 12-layer and 16-layer stacking, the increase in stacking height will make yield and thermal management more difficult. Infomarket proposes another idea: arrange more HBM stacks horizontally around the GPU, instead of relying entirely on increasing the height of a single stack to increase capacity.

In this case, the packaging structure needs to accommodate more chips and memories distributed horizontally. The reference believes that glass may become a suitable supporting material to achieve circuits with a linewidth of about 2 microns on a structure about 30cm wide while controlling warpage.

The expansion of packaging size will also bring interconnection problems. When the distance between the GPU and the memory continues to increase, the signal integrity of copper interconnection will face greater pressure. The reference points out that at frequencies of tens of GHz, even a copper interconnection distance of only a few centimeters may be significantly limited.

Therefore, optical interconnection is expected to become an option for connecting chips and memories at relatively long distances. Glass can accommodate optical waveguides, which also provides a potential foundation for optical interconnection integration.

According to Infomarket's judgment, the industry may first develop a large-size glass packaging platform, and then gradually introduce optical interconnection. In other words, the demand for optical interconnection not only involves optical devices themselves, but also may affect the material selection and structural design of the packaging platform.

Where Does the Market of Tens of Trillions of Won Come From?

The ultimate scale of equipment opportunities depends on the demand scale of advanced packaging and whether the process transformation can be truly implemented.

The calculation scenario given by Infomarket is: assuming that Nvidia ships millions of Rubin-generation GPUs in 2027, and each GPU package is equipped with 8 sets of HBM stacks. If the costs of interposer, packaging substrate, bonding, dicing and inspection are included, the cost of a single package can reach thousands of US dollars, and the corresponding annual packaging market scale may reach tens of trillions of won.

This is an estimate based on shipment volume and packaging cost assumptions, not the already realized market revenue.

But this also explains why panel-level packaging has attracted widespread attention. For large packages that need to integrate GPUs and multiple sets of HBM, improving the panel area utilization rate is only one of the considerations; as the packaging structure becomes larger, the process requirements for mounting, dicing, inspection and substrate connection will also change accordingly.

If the development continues toward the permanent glass structure in the follow-up, the industry may usher in the second round of equipment investment. In terms of materials, the demand involves glass carriers, release layers, ultra-thin copper foils, dielectric films, molding compounds, glass core materials and TGV-related materials; in terms of equipment, it includes TC bonders, MSVP, laser stripping equipment, panel photolithography equipment and electroplating systems.

Infomarket mentioned that a Korean supplier has received orders for large-area TC bonders and shipped them to Taiwan, while starting to supply precision MSVP equipment to Samsung Electro-Mechanics and LG Innotek. The original text does not disclose the specific name of this supplier and the order amount.

From the perspective of a larger industrial layout, advanced packaging capacity is also extending to the United States. TSMC has announced plans to build two packaging facilities in Arizona, Amkor is developing packaging projects locally, and SK Hynix is building an HBM packaging facility in Indiana. For projects that hope to build AI chip manufacturing capabilities from scratch, advanced packaging is also a key link that needs to be considered.

Final Notes

The change brought by CoPoS is not just replacing wafers with panels, but making advanced packaging face larger processing areas, more complex material combinations, and stricter requirements for warpage control and inspection.

At present, the 40mm-class TC bonder, MSVP and 120mm-class TC bonder are the most direct equipment opportunities in this process. Looking further ahead, whether glass core substrates and glass interposers can achieve mass production will determine whether the demand for equipment and materials will usher in a new round of changes.

Infomarket believes that with the expansion of the packaging market and the transformation of production methods, the relevant market scale is expected to further grow from tens of trillions of won to hundreds of trillions of won. This judgment still depends on future shipment volume, process routes and industrialization progress, but the two proposed change paths are worthy of attention: first shift from wafers to panels, and then evolve from organic structures to permanent glass structures.

For equipment and material suppliers, the real test is whether they can keep up with the process changes and solve practical problems in links such as large-area precision bonding, panel dicing, glass processing and mass production inspection. Whoever can take the lead in meeting these requirements will have more opportunities to participate in the construction of the next stage of advanced packaging production lines.

This article is from the WeChat official account "Semiconductor Industry Observation" (ID: icbank), written by the editorial department, and authorized for release by 36Kr.