Samsung HBM: Has It Come From Behind to Take the Lead?
The competition for next-generation HBM is extending from DRAM chip performance to advanced packaging processes.
According to a report by Damnang on October 7, based on interviews with relevant technical personnel, SK Hynix has encountered difficulties in the development of next-generation HBM hybrid bonding technology, while Samsung Electronics is reportedly starting to deliver samples using this technology to customers. If this news is further confirmed, Samsung is expected to take the lead in the advanced packaging technology verification phase of next-generation HBM.
However, this information does not come from the official announcements of the two companies, but is based on interviews with technical personnel and relevant second-hand reports. The report does not clearly specify the HBM generation, number of stacked layers and customer information involved, so it is not sufficient to judge the actual R&D gap between the two sides, let alone conclude that Samsung has taken a comprehensive lead in the next-generation HBM competition based on this.
More importantly, SK Hynix's progress in hybrid bonding technology is not equivalent to the development progress of its next-generation HBM products.
On June 18, SK Hynix announced that it has delivered 12-layer HBM4E samples with a capacity of 48GB to major customers, adopting its existing Advanced MR-MUF packaging technology. The company stated that compared with HBM4, the thermal resistance of this product has been improved by 17%.
This means that even if the development of hybrid bonding faces difficulties, SK Hynix is still advancing the development of next-generation HBM products along the existing packaging route. The real problem worthy of attention is: when HBM develops towards a higher number of stacked layers, to what extent can the traditional packaging process meet the requirements of performance, heat dissipation and packaging height, and what manufacturing thresholds does hybrid bonding need to cross to achieve large-scale production.
Why has hybrid bonding become an important direction for next-generation HBM?
HBM provides high-bandwidth memory for GPUs and AI accelerators by stacking multiple DRAM chips vertically. As the scale of AI models continues to expand, HBM not only needs to increase capacity and bandwidth, but also must control power consumption and heat generation within a limited packaging space.
At present, traditional HBM stacking usually uses Micro Bumps to connect the upper and lower chips, and handles the chip gap through relevant filling and protective material processes. SK Hynix's Advanced MR-MUF is a representative of this technical route, which improves the reliability and heat dissipation performance of the stacked structure by optimizing the Micro Bump connection and the filling and curing process of liquid protective materials.
Hybrid bonding attempts to further reduce reliance on Micro Bumps. This technology directly connects the copper interconnection structures on the surfaces of the upper and lower chips, and at the same time bonds the surrounding dielectric insulation layers to each other, thereby reducing the space occupied by the traditional interconnection structure.
Its advantages lie in that the smaller interconnection pitch and shorter electrical connection distance are expected to increase interconnection density, reduce signal transmission loss, and create conditions for higher-density DRAM stacking. Reducing some intermediate materials in the bonding interface is also expected to improve heat conduction.
As HBM develops from 12 layers to 16 layers or even higher, the space constraint between chips and heat dissipation pressure will become more prominent, and the potential value of hybrid bonding will also increase accordingly.
Samsung introduced the hybrid copper bonding technology HCB in a release for GTC-related events on March 17, positioning it as a technical solution to support next-generation HBM with 16 layers and above. Samsung said that compared with traditional Thermal Compression Bonding (TCB), HCB is expected to reduce thermal resistance by more than 20%.
This technical direction echoes the statement on the sample progress in this report, but technical demonstration does not mean that the product has been mass-produced. The thermal resistance improvement announced by Samsung cannot be directly ranked with SK Hynix's data that HBM4E has improved by 17% compared with the previous generation: the former compares the bonding methods, while the latter compares products of different generations, and the comparison benchmarks of the two are not the same.
The real difficulty is to make the bonding process stable and repeatable
The manufacturing difficulty of hybrid bonding is far more than just aligning and bonding two chips with high precision.
According to the process interpretation from Applied Materials, Chemical Mechanical Planarization (CMP) is one of the key links. Manufacturers need to precisely control the height relationship between copper pads and the surrounding dielectric layer to make the bonding surface meet the nanometer-level flatness requirement.
If the copper surface is too deeply recessed, the upper and lower copper structures may not be in full contact; if the copper surface protrudes too much, it may interfere with the dielectric layer bonding and increase the risk of interface defects. Therefore, the flatness of the bonding surface, the height of the copper pads and the consistency of the entire area must be strictly controlled.
At the same time, particles generated during grinding and chip dicing, surface contamination, and changes in surface properties over time after activation may affect the bonding quality. This requires manufacturers to collaboratively manage cleaning, surface treatment, environmental cleanliness and the bonding time window.
In other words, hybrid bonding cannot be solved by purchasing a high-precision bonding equipment alone. Links such as grinding, cleaning, inspection, chip alignment and bonding must form a stable process chain to convert the successfully bonded products in the laboratory into repeatable mass production results.
The structural characteristics of HBM itself further increase the difficulty.
In order to control the packaging height while increasing the number of stacked layers, DRAM chips need to be continuously thinned. However, the thinner the chip, the more vulnerable it is to warpage under mechanical stress, which in turn increases the risk of position deviation and bonding defects. As the number of stacked layers increases, multiple bonding interfaces also mean more potential failure points.
However, there is currently no reliable information indicating which specific process SK Hynix has encountered difficulties in. CMP, surface contamination and chip warpage are common manufacturing challenges faced by hybrid bonding, and cannot be directly identified as the reasons for the development setback this time.
From technical verification to mass production, there is still a yield barrier to cross
The industrialization of hybrid bonding also depends on the specific chip bonding method.
imec previously demonstrated Wafer-to-Wafer bonding technology, which aligns and bonds two wafers as a whole. This method can process a large number of chips at one time, but if defective chips are also bonded together, the overall yield may be affected.
Another method is Die-to-Wafer bonding, which is to screen qualified chips first, and then place them one by one on the target wafer to complete the bonding. Its advantage is that it can prioritize the use of good chips that have been tested, but picking, positioning and bonding each chip one by one will also bring challenges to production efficiency.
The relevant interpretation by Professor Seunghwan Joo of Inha University published on SK Hynix's news center points out that Die-to-Wafer bonding is developing towards the commercial application of HBM. This shows that the bonding accuracy proved by wafer-level experiments is not the same issue as the yield and production efficiency required for multi-layer stacking of HBM.
Equipment manufacturers are also improving the process chain around this manufacturing challenge.
On October 1, Applied Materials and Besi announced the expansion of their cooperation in the field of advanced packaging. The two parties combine Applied Materials' process technologies in grinding, cleaning, metrology and inspection with Besi's chip placement and bonding technologies. One of the relevant achievements is Kinex, an integrated Die-to-Wafer hybrid bonding system.
This cooperation reflects that the competition of hybrid bonding is extending from the precision of a single equipment to the process integration capability before and after bonding. However, existing materials do not indicate that Samsung or SK Hynix has adopted this system.
For HBM manufacturers, the real challenge is to keep every bonding interface stable, meet the product reliability requirements after multi-layer stacking, and control production efficiency and manufacturing costs within an acceptable range. Successfully bonding samples is only the first step.
Can Samsung's sample advantage be translated into mass production competitiveness?
If the information in this report is true that Samsung has delivered hybrid bonding HBM samples to customers, its advantages are first reflected in the R&D and customer verification process. Earlier access to customer testing helps to discover problems in bonding reliability, heat dissipation and system integration in advance, and accumulate experience for subsequent product development.
However, there is still a distance between sample delivery and mass production. The progress of customer certification, mass production yield, manufacturing cost and available supply scale are the key indicators to judge whether technical advantages can be translated into commercial competitiveness.
At the same time, SK Hynix has promoted the delivery of HBM4E samples through Advanced MR-MUF, indicating that the traditional packaging route is still playing a role. The new hybrid bonding does not mean that the existing process will exit the market immediately. The two routes can develop in parallel, and the specific choice depends on product performance requirements, manufacturing capabilities and mass production economy.
Therefore, it is not possible to conclude that Samsung has taken a comprehensive lead based on only one interview report at present, nor can SK Hynix's difficulties in hybrid bonding be equated with the stagnation of its HBM product development.
In the next stage, it is more worthy of attention on which generation of HBM and products with how many stacked layers the two sides respectively introduce hybrid bonding, and whether there are substantial differences in customer certification, mass production schedule and yield performance.
The HBM competition is shifting from simply increasing the number of stacked layers to a systematic competition involving memory design, bonding process, heat dissipation management and advanced packaging. Hybrid bonding is expected to further unlock the potential of high-density stacking, but what ultimately determines its industrial value is not whether a batch of samples can be successfully manufactured, but whether it can translate technical advantages into sustainable delivery capabilities with stable yield, reasonable cost and sufficient production capacity.
Final Notes
In fact, behind this news, there is another level of information hidden, that is, the substantial increase in Samsung's HBM market share.
First of all, we must admit that in the current HBM shipments dominated by HBM3E and HBM4, SK Hynix is the leading manufacturer with a 50% market share. But we also see that SK Hynix's market share has declined slightly, as the company previously accounted for as high as 64% of global HBM memory spending.
However, according to data from Counterpoint Research, Samsung's share in the HBM market rose from 21% in the first quarter to 33% in the second quarter, which brought SK Hynix's share down to 30%. It is expected that this share will further expand as HBM4 shipments increase in the second half of the year. The market expects that by 2027, the price of Samsung's HBM products will more than double compared with this year, and its product contract price is the highest among the three major memory manufacturers including SK Hynix and Micron. Data from KB Securities shows that by 2027, the proportion of HBM4 products in Samsung's HBM sales is expected to double from 40% this year to 80%.
It can be seen that Samsung seems to have staged a beautiful comeback in the HBM field.
This article is from the WeChat Official Account "Semiconductor Industry Observation" (ID: icbank), authored by the Editorial Department, and authorized for release by 36Kr.