Everyone is scrambling for chip companies.

In the past, the industry was accustomed to directly purchasing off-the-shelf chips. Today, GPU enterprises, cloud vendors, and AI large model companies are all using equity, long-term agreements, capital investment and other methods to deeply bind supply chain enterprises. This is no longer a simple act of "buying and stocking up on chips". What the giants are competing for is not only the computing power available at present, but also the production capacity quotas, chip customization capabilities and the right to speak in system-level technologies in the coming years.

Three Types of Players Launch a Chip Grabbing Battle

Facing the tight supply of the computing power supply chain, GPU vendors, cloud service providers, and AI large model enterprises have different resources and situations, which have led to the evolution of different layout strategies.

Major GPU Vendors: Complete the System Landscape Through Mergers and Acquisitions

For chip vendors such as NVIDIA and AMD, investing in chip startups is not only to strengthen individual products, but also to build complete system capabilities around computing clusters.

NVIDIA has signed a non-exclusive inference technology licensing agreement with Groq. With this cooperation, NVIDIA has obtained technologies related to LPU inference chips and launched the Groq 3 LPU product. In addition, NVIDIA has also participated in the investment of optical interconnection startups AyarLabs and Hark. In July this year, according to Bloomberg reports, NVIDIA made a strategic investment in SSI, the AI lab founded by Ilya, opened the Vera Rubin computing platform to SSI, so as to deeply bind the cutting-edge R&D team and obtain real business feedback.

AMD has adopted a route of multiple mergers and acquisitions superimposed with large equity binding of business parties. The completed acquisitions include: AI software vendor SiloAI, server system vendor ZT Systems, and near-storage computing enterprise MEXT. In August this year, AMD also signed a final acquisition agreement with inference chip enterprise Taalas to strengthen its technical layout in AI inference.

Cloud Vendors: Write Production Capacity into Contracts Through Equity

If GPU vendors layout chip resources to consolidate their own hardware ecosystem, then for cloud service providers, the goal is to build a supplier portfolio that can continuously control the scale and cost of computing power.

According to supply chain sources, Google has renewed a long-term supply agreement with Broadcom, extending the cooperation to 2031, covering TPU and supporting network components; in August, Marvell granted Google warrants with a potential maximum exercise value of 12.2 billion US dollars, further expanding the scale of various cooperations with Google. As for Meta, after completing the acquisition of Rivos, it used its RISC-V core in the third-generation self-developed chip MTIA. In July 2026, news came out that Meta would hand over the iterative order of MTIA to Samsung's 2nm production line, with a potential order size of more than 10 trillion won.

AWS's layout idea is different. On the one hand, it strategically bets on Anthropic and promotes the self-developed Trainium3 chip, on the other hand, it purchases Cerebras wafer-level chips to carry out multi-path computing power layout.

Large Model Companies: Bind Themselves Deep into the Supply Chain

Compared with chip giants and cloud service providers with strong capital strength, AI large model companies are located downstream of the industrial chain and are themselves large consumers of computing power. Their strategy is to embed deeper into the semiconductor supply chain system.

Anthropic is a relatively active AI enterprise in this wave. It has signed a 3.5GW TPU computing power agreement with Google and Broadcom at the same time to jointly build a computing power cluster; in June this year, it reached a cooperation with Micron to jointly deploy the large-scale implementation of AI infrastructure; in August, it announced the purchase of Fractile's AI ASIC chips. OpenAI's actions are equally intensive: binding AMD, purchasing custom computing power from Cerebras, and cooperating with Broadcom to promote the custom chip project codenamed Jalapeño, reducing dependence on a single chip supplier to obtain exclusive computing power adapted to its own large model.

Why Are Companies Scrambling to Acquire Chip Companies

Enterprises are intensively using capital means such as acquisitions, equity investments, and long-term procurement to bind chip companies, which is driven by multiple practical contradictions in computing power supply and demand, technological iteration and supply chain security.

The first reason is the cycle mismatch between computing power planning and production capacity construction, and spot transactions are gradually shifting to the reservation quota model. According to Goldman Sachs' calculation, the overall scale of global AI-related investment will exceed 1 trillion US dollars in 2026, and the capital expenditure of large cloud service providers on computing power infrastructure will reach the range of 725-760 billion US dollars, with the related investment scale expanding rapidly. However, in contradiction with this, the pace of production capacity construction cannot keep up with the growth of demand at all.

Computing power demand grows rapidly quarter by quarter, while supply release is calculated on an annual basis, forming a huge time gap between the two. Pure spot procurement can no longer match the 3-5 year computing power planning of giants. Therefore, options, long-term agreements, and capital binding linked to procurement performance have become important tools for locking in future supply.

The second reason is that everyone wants to grab the computing power itself. According to statistics, in the global data center accelerated chip market in 2026, general-purpose GPUs still occupy the vast majority of the market share, and the shortage of chips makes the entire industrial chain queue up for supply. Even NVIDIA needs to compete for upstream suppliers, which shows the tightness of the entire supply chain.

The third reason is more critical: the focus of performance improvement has shifted to the system level, and customized chips are ushering in rapid growth. Moore's Law is gradually approaching the physical limit, the performance improvement space of a single chip is narrowing, and the importance of the coordination efficiency between chips is becoming increasingly prominent, such as high-speed interconnection, memory bandwidth, near-memory computing, network controllers and other system links. A SEMI executive said in a public speech that the proportion of AI infrastructure expenditure related to inference in 2026 has exceeded 70%. The load characteristics of such businesses further amplify the cost advantage of customized chips. To obtain the next-generation performance advantage, enterprises cannot completely rely on standardized finished products on the market, and need to deeply participate in the design and definition of chips.

The fourth reason comes from the industry's fear of geopolitics and single-point supply chain risks. The HBM market is dominated by three companies: Samsung, SK Hynix, and Micron, which together account for the vast majority of the market share; high-end 2-3nm logic foundry and CoWoS advanced packaging production capacity are also concentrated in a few manufacturers. Once the supplier experiences fluctuations in yield, certification, geopolitical environment and other aspects, the downstream business will be directly impacted. This has also formed a consensus in the market: it is highly risky to bet all resources on a single supplier, and building multiple parallel supply chains has become a strategic choice for enterprises.

Is It Worth Making Capital Layout in Chip Enterprises

News of tech giants making large-scale layouts in chip enterprises keeps emerging, and the market seems to generally default that such transactions are a sure bet. However, a careful calculation of commercial costs shows that benefits and risks exist at the same time.

For tech giants, such a layout can bring definite commercial benefits. First of all, cost optimization can be achieved by co-developing ASICs with chip companies. Taking Meta as an example, its self-developed chips are designed to replace outsourced general-purpose GPUs. Sufficient computing power demand can effectively spread the R&D and mass production investment of chips, so that the cost advantage of self-developed customization can be fully realized. In addition to preemptively locking in chip and memory production capacity through capital intervention, it can also indirectly raise the entry barriers for peers and build competitive advantages.

However, behind the seemingly lucrative transactions, there are also many hidden dangers. A large number of mergers and acquisitions superimposed with tens of billions of dollars of equity arrangements will continuously expand the management boundary of enterprises, and the financial pressure will also rise accordingly. Chip projects are highly dependent on the core R&D team. Once the core talents leave after the acquisition is completed, the value of the previous investment will be greatly reduced. At the same time, most highly customized chips are developed around the enterprise's own business needs, and do not have the flexible secondary circulation space of general-purpose GPUs. If the subsequent business demand fails to meet expectations, these highly dedicated hardware assets may turn into asset burdens. What is more worthy of vigilance is the local bubble risk brought by mutual investment and mutual procurement between upstream and downstream parties.

Where Is the Next High Ground for Competition

After leading players complete the competition for chip design companies and customized chip orders, the competition does not stop there. The computing power competition is continuing to spread upward along the supply chain. Even if many enterprises get the chip design scheme, they still cannot achieve large-scale implementation without the corresponding manufacturing resources and production equipment.

The areas where competition has become white-hot at present are concentrated in advanced process and advanced packaging production capacity. Various customized chips such as GPU, TPU, and inference ASIC are competing for limited packaging production capacity. Advanced packaging has replaced part of the wafer process and become a key bottleneck restricting the delivery of AI chips. Followed by semiconductor equipment and core materials, the supply of high-end ABF packaging substrates and high-speed PCBs is tight, and the delivery cycle of some high-end materials exceeds half a year. In addition, the value of software toolchains such as chip compilation, driver, and testing continues to be prominent. Without the support of a mature software stack, it is difficult for hardware performance to be fully released.

Looking further into the future, industrial competition will further spread in the next 3-5 years. The first is the standards and mass production capabilities of high-speed interconnection and optical interconnection systems. As the computing power of a single chip continues to increase, data transmission between chips has gradually become the main shortboard of cluster performance. From traditional pluggable optical modules to silicon photonics and CPO co-packaged optics routes, whoever can dominate the next-generation interconnection specification will directly determine the operating efficiency of the entire computing cluster. However, this track is not only related to the selection of technical solutions, but also limited by practical production capacity constraints: there are manufacturing barriers in high-speed laser yield, optical fiber array components, and optoelectronic hybrid packaging. The expansion pace of optical interconnection hardware will directly affect the expectation of large-scale implementation.

In addition, the bottleneck brought by the "memory wall" will be another key direction that the industry needs to overcome. The existence of the "memory wall" causes a large amount of computing power to be consumed in data movement rather than actual calculation. Computing-in-memory and near-memory computing are regarded by the industry as the direction to break the deadlock. However, to achieve real implementation, relying solely on chip architecture innovation is far from enough, and supporting special storage processes, new packaging schemes, and new software compilers are also required for coordinated adaptation.

Another point is that the current industry's computing power planning of 2GW or 10GW makes the construction of underlying physical infrastructures such as computing power and heat dissipation increasingly important. According to IEA data, the power consumption of data centers dedicated to carrying AI services was about 155 TWh in 2025, and it is expected to grow to more than 465 TWh in 2030, more than tripling in five years. The power density of a single cabinet of the new generation of AI cabinets has increased significantly. Traditional air cooling can no longer meet the heat dissipation requirements. Liquid cooling, high-voltage power supply, and stable power grid supporting facilities have become the hard thresholds for the implementation of large-scale intelligent computing clusters.

Closing Remarks

Looking through the dazzling equity agreements and commercial orders, this wave of scrambling for chip companies illustrates a phenomenon: whoever holds production capacity and design capabilities holds the pricing power. At the same time, we can also see that capital can acquire chip teams and sign long-term agreements, but cannot avoid the test of manufacturing processes, talent accumulation and real business demand. Whether all this is worthwhile can only be truly judged after the customized projects are successively put into production, to see whether they are buying the dip in the future of the industry or reinforcing the industry bubble.

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This article comes from the WeChat official account "Semiconductor Industry Watch" (ID: icbank), author: Xia Xue, published with authorization from 36Kr.