TSMC won the bet again
A notable change is taking place in Samsung Foundry's advanced process technology roadmap.
Samsung originally planned to achieve mass production of the 1.4nm process in 2027, but this timeline has now been adjusted to 2029. In other words, before moving to 1.4nm, Samsung will continue to expand and optimize around the 2nm process, and focus on process maturity, yield improvement and customer onboarding in the coming years. As early as 2022, Samsung announced the plan to mass produce 1.4nm in 2027, and the delay to 2029 means that this goal is two years later than the original plan. From now to 2029, Samsung will need to continue to deepen its efforts on the 2nm platform for three more years.
Samsung has previously adopted a relatively aggressive strategy for advanced processes, especially taking the lead in adopting GAA (Gate-All-Around) transistors at the 3nm node, hoping to build differentiated advantages and catch up with TSMC through faster node iteration. However, after entering the 2nm era, the technical difficulty and capital investment of advanced processes are rising rapidly, and the competition is no longer simply about "who enters the next node first".
For wafer foundries, whether a new process node can truly create value ultimately depends on yield, performance, power consumption, number of customers and mass production cost. Therefore, instead of pushing 1.4nm prematurely, it may be a more realistic choice for Samsung to first mature the 2nm platform and then extend its commercial life cycle through different derivative processes.
In fact, Samsung is not "standing still" on 2nm. In addition to the standard SF2, Samsung is also promoting 2nm derivative processes for different application scenarios, and plans to introduce technologies such as backside power delivery in more advanced versions. For AI and HPC chips, as the die size continues to expand and power consumption continues to rise, the power delivery network has become an important factor affecting performance. Therefore, what Samsung really needs to solve in the coming years is not "how to make 1.4nm as soon as possible", but how to make 2nm a more mature, reliable and mass-producible platform.
Why is Samsung in no hurry to adopt High-NA EUV?
It is worth noting that Samsung has not rushed to take High-NA EUV, that is, high numerical aperture extreme ultraviolet lithography, as a mandatory technology for 2nm and 1.4nm mass production. Park Chang-min, Vice President of Samsung Electronics Technology, previously stated that the company hopes to apply High-NA EUV to mass production of advanced nodes such as 2nm and 1.4nm in the future, but this technology still needs further maturity. Samsung believes that starting from A10 and below, that is, nodes at the 1nm level and more advanced, High-NA EUV may truly become a necessary technology for advanced process mass production. At present, Samsung is carrying out joint development with industry chain partners.
The biggest advantage of High-NA EUV is that its higher numerical aperture can further improve lithography resolution, thereby reducing some complex multi-patterning processes and providing support for more advanced transistor manufacturing. But the problems are also obvious: the price of High-NA EUV equipment is very expensive, and the exposure field of view is smaller than that of traditional EUV, which may bring more stitching requirements for AI and HPC chips with larger and larger areas. At the same time, supporting links such as photoresist, mask, pellicle and computational lithography also need to be upgraded synchronously. Therefore, for wafer fabs, High-NA EUV is not simply "the more advanced the technology, the better", but a long-term investment that requires comprehensive consideration of equipment cost, chip area, yield, production capacity and PPA benefits.
This is also one of the important reasons why Samsung does not currently regard High-NA EUV as a mandatory technology for 1.4nm mass production. For Samsung, if the 1.4nm process can still be achieved through the mature Low-NA EUV system, there is no need to prematurely bear the additional cost and process complexity brought by High-NA EUV in pursuit of higher lithography resolution. In contrast, waiting for High-NA EUV to further mature and reserving its value for 1nm-level and below nodes may be a more pragmatic choice.
Advanced Processes Enter the "Era of Cost Accounting"
From this perspective, Samsung's delay of 1.4nm does not mean that the competition in advanced processes is slowing down. On the contrary, it indicates that the industry is entering a new stage. Over the past decade, the core of advanced process competition has been "who enters the next node first". From 28nm, 16/14nm, 10nm, 7nm, 5nm to 3nm, the node number itself is an important embodiment of the technical strength of wafer fabs. However, at 2nm and below, the cost of simply pursuing node scaling is getting higher and higher. New technologies such as GAA, backside power delivery, EUV and High-NA EUV all require huge R&D and capital investment, but the performance and density improvement brought by each generation of process may not maintain the magnitude of the past.
At the same time, the real difficulty of advanced processes is no longer just "making it", but "making it stably". Especially for AI GPU and HPC chips, the die size is constantly expanding, and the larger the chip area, the higher the requirement for wafer manufacturing yield. Even if a process can achieve higher transistor density, if the yield ramps up slowly and the wafer cost is too high, customers may not be willing to adopt it in the end. Therefore, what wafer fabs need to calculate now is not only how much the transistor density increases and how much the performance improves, but also how many valid chips can be produced from each wafer, and whether customers are willing to pay a higher price for these performance improvements.
More importantly, the value of advanced processes no longer only comes from transistor scaling. Chiplet, 3D stacking, HBM and advanced packaging are all becoming important means to improve the performance of AI chips. The final performance of an AI chip depends on multiple links such as computing die, HBM, interconnection, power delivery, heat dissipation and packaging. Therefore, the competition for advanced processes in the future will essentially shift from a simple "node race" to a comprehensive competition of technology, cost and ecosystem. Samsung's extension of the 2nm life cycle can be seen as rebalancing technological progress and commercial returns, on the premise that it must truly improve the 2nm yield and customer scale in these three years.
TSMC's A16 Leadership
The problem is that while Samsung is slowing down, TSMC has not stopped to wait. TSMC's N2 has entered mass production, and its first post-2nm node A16 is also scheduled to enter mass production in the second half of 2026. This means that while Samsung is still further improving the 2nm family, TSMC has begun to move towards the 1.6nm level.
One of the biggest changes of A16 is the introduction of TSMC's SPR (Super Power Rail) backside power delivery technology. In traditional chips, power lines and signal lines are mainly concentrated on the front side of transistors. As the process size continues to shrink, front-side routing resources are becoming increasingly tight, and resource competition between the power network and the signal network is becoming more and more serious, which further brings problems such as routing congestion and IR Drop. Backside power delivery transfers the power path to the back of the chip, releasing more front-side routing resources for signal transmission, while shortening the power path and reducing power supply impedance, thereby improving power delivery efficiency under advanced processes.
Data released by TSMC shows that compared with N2P, A16 can increase speed by 8% to 10% at the same power consumption level, reduce power consumption by 15% to 20% at the same speed, and increase chip density by up to about 10%. This means that the significance of A16 is not only to advance the node from 2nm to 1.6nm, but to further release the performance potential of advanced processes through backside power delivery. Especially for AI and HPC chips, as the chip size continues to expand and power consumption continues to rise, the importance of power integrity and signal integrity is no less than that of the transistor itself.
In fact, backside power delivery has become an important technical direction for advanced processes at 2nm and below. Intel introduced PowerVia in 18A, TSMC adopted the SPR scheme in A16, and Samsung is also promoting related technologies. It can be seen that the competition for advanced processes has expanded from the transistor structure itself to the collaboration of power delivery, interconnection, design and manufacturing processes.
It is particularly worth mentioning that TSMC previously stated that it will maintain a cautious attitude towards High-NA EUV. Judging from Samsung's this delay, TSMC has won the bet again.
Final Notes
Samsung's 2nm roadmap in the next three years is actually facing considerable pressure. On the one hand, it needs to continue to improve the yield of the 2nm process and the speed of customer onboarding; on the other hand, it must also face the continuous advancement of TSMC's A16 and subsequent more advanced nodes. By 2029, when Samsung truly launches 1.4nm, TSMC and Intel will most likely have entered a new technical stage.
This also means that the future competition in advanced processes can hardly be simply measured by numbers such as "2nm, 1.4nm, 1nm". Technologies such as GAA, backside power delivery, EUV, High-NA EUV, DTCO and advanced packaging will jointly determine the final performance and cost of a chip. The competition for advanced processes is shifting from "who has a more advanced node" to "who can turn advanced technologies into large-scale products with more reasonable costs".
Samsung is not abandoning 1.4nm, but using the next three years to truly mature the 2nm process, achieve large-scale production and expand its customer base. But the question also arises: when Samsung truly moves to 1.4nm in 2029, where will TSMC and Intel be, which is perhaps the most noteworthy part of this advanced process competition.
This article is from the WeChat official account "Semiconductor Industry Watch" (ID: icbank), written by the Editorial Department, and published with authorization from 36Kr.