The United States is betting on the "post-GPU era"

The strategy of U.S. chip hegemony is shifting from "reshoring production capacity" to betting on next-generation new technologies.

On July 29, the U.S. Department of Commerce signed letters of intent with seven companies for a total amount of up to 874 million U.S. dollars. Unlike the early subsidies that mainly focused on wafer fab construction, this fund is not concentrated on expanding production of advanced processes. Instead, in the form of VC (Venture Capital), it takes equity stakes in seven disruptive technology companies, making a full bet on the seven underlying technology routes in the "post-GPU era".

Looking through the technology lists of these seven enterprises, this is by no means a routine industrial support, but a "technology encirclement and hunting" campaign aimed at comprehensively deconstructing and reshaping the polar axis of the semiconductor industry from materials, physical mechanisms, packaging to AI storage. The seven companies cover CPO, ferroelectric memory, 3D packaging, low-loss dielectric, thermodynamic computing, chip anti-counterfeiting and new optoelectronic substrates respectively.

Enterprises that finally obtain the funds also need to provide the U.S. government with a minority stake without control rights. This also means that the U.S. authorities have completely broken the illusion of non-intervention in the free market, binding national will with capital.

GlobalFoundries: Blocking Chinese optical modules while supplementing U.S. CPO capabilities

Among the seven projects, the one with the largest amount of funding goes to GlobalFoundries.

The U.S. Department of Commerce plans to provide it with up to 300 million U.S. dollars to advance the R&D progress of CPO technology in the United States by two to three years.

With the large-scale deployment of 800G, 1.6T, CPO and silicon photonics, optical interconnection is no longer an ordinary communication component, but an integral part of the AI computing power system. The core idea of CPO is to move the optical engine further from the pluggable module to the vicinity of the switching chip or AI processor, shorten the transmission distance of high-speed electrical signals, and reduce the loss and power consumption caused by long-distance copper interconnection.

In recent years, GlobalFoundries has been vigorously developing silicon photonics. It aims to build end-to-end capabilities in the United States covering silicon wafers, optical device manufacturing, advanced packaging and tested optical modules.

In November 2025, the company acquired Singapore-based silicon photonics foundry Advanced Micro Foundry. GlobalFoundries stated that AMF has more than 15 years of experience in silicon photonics manufacturing, adopts a 200mm platform, and plans to expand to 300mm according to market demand. This transaction further expands GlobalFoundries' silicon photonics manufacturing capacity and customer coverage. In the same period, GlobalFoundries also acquired high-speed connection chip design company Infinilink, obtaining SerDes, optical transceiver chipset and monolithic silicon photonics design capabilities.

In May 2026, GlobalFoundries released the SCALE CPO platform, which integrates silicon photonic devices, wavelength division multiplexing, photodetectors, TSV and 2.5D, 3D stacking interfaces. The company defines it as the first CPO platform compatible with the OCI MSA specification, supporting CWDM, DWDM, silicon-germanium integration and advanced packaging.

GlobalFoundries has set itself the goal of increasing the data transmission speed to 400Gbps, and striving to achieve an energy efficiency improvement of up to about 5 times compared with current solutions.

On the one hand, it is promoting the industrialization of domestic silicon photonics, and on the other hand, it is restricting the supply status of Chinese enterprises in the current pluggable optical module market.

On August 4, Reuters reported that the U.S. Federal Communications Commission is drafting restrictions on Chinese data center devices, which may focus on new models of Chinese optical transceiver modules. The relevant plan has not been finalized and may still be modified, but the United States hopes to launch it within 2026.

Aeluma: Large-size optoelectronic substrates without indium phosphide

Aeluma will receive up to 30 million U.S. dollars, which complements the upstream material link of the silicon photonics strategy. Founded in 2019, Aeluma is currently listed on NASDAQ.

Traditional high-performance photodetectors and lasers often rely on compound semiconductor substrates such as indium phosphide, but indium phosphide wafers are small in size, with limited manufacturing cost and expansion capacity. Aeluma tries to heterogeneously integrate compound semiconductor materials on large-size substrates, so that optoelectronic devices can use processes and equipment closer to mainstream silicon manufacturing.

The company disclosed that its technology can manufacture optoelectronic devices on substrates up to 12 inches, while traditional indium phosphide devices usually mainly use 2-inch to 4-inch substrates. The U.S. Department of Commerce clearly requires Aeluma to develop large-diameter optoelectronic substrates that do not rely on indium phosphide for lasers and photodetectors in AI optical interconnection.

This shows that the United States is not betting on an isolated CPO product, but a complete chain from materials, wafers, silicon photonic devices to packaging and testing.

Kepler: Using "ferroelectric technology" to break through the memory wall

The second largest amount of funding goes to Kepler. The U.S. Department of Commerce plans to provide up to 245 million U.S. dollars to support its development of new high-performance AI memory based on 3D structure and ferroelectric technology.

Kepler Computing was founded in 2018, and its founder is Debo Olaosebikan. Public investment materials show that the company has long studied ferroelectric materials, low-voltage logic, and 3D integrated memory and computing architectures.

The reason behind this is not difficult to understand. The core problem of AI computing is no longer just the speed of multiply-add operations. Model parameters, activation values and intermediate data need to be constantly moved between computing units and storage units. The time and energy consumed by data migration are eroding the benefits brought by GPU performance improvement.

HBM alleviates the bandwidth problem, but at the cost of expensive advanced packaging, complex stacking processes and limited supply capacity. Traditional DRAM is fast, but it needs to be refreshed continuously; NAND has large capacity and low cost, but its latency and write performance cannot meet the needs of high-performance computing.

Ferroelectric memory tries to find a new position between these traditional hierarchies. Ferroelectric memory stores information through the polarization state of materials, retains data after power off, and has the potential of low voltage and fast switching.

In the industrial field, the hafnium oxide ferroelectric memory recently demonstrated by Fraunhofer and GlobalFoundries can work at a voltage lower than 1V and complete switching at the nanosecond level; CEA-Leti has also demonstrated a 3D ferroelectric capacitor structure at the 22nm node, hoping to increase density through vertical stacking.

Kepler is mainly focusing on the combination of 3D and ferroelectrics. If ferroelectric memory can only be used as embedded memory with small capacity, its impact is mainly limited to MCUs, edge AI and low-power devices; but if density can be increased through 3D stacking and deployed near AI accelerators, it can undertake part of the tasks of cache, persistent memory or near-memory computing.

The U.S. government's investment of 245 million U.S. dollars at this time does not mean that ferroelectric memory has won, but hopes to keep R&D, trial production and intellectual property rights in the United States before the technical route is finalized.

Advanced packaging becomes a top priority

Multibeam and Thintronics receive a total of up to 190 million U.S. dollars. These two companies are small in scale, but they correspond to two easily overlooked bottlenecks in advanced packaging: patterning and insulating materials respectively.

As transistor miniaturization becomes more and more expensive, the patterning accuracy, interconnection distance and material loss in advanced packaging are becoming new means of performance scaling.

First, let's take a look at Multibeam, which has an impressive background. The founder and CEO David K. Lam is exactly the founder of Lam Research. In 1980, he founded Lam Research and launched the early single-wafer plasma etching system.

Multibeam's core product is the multicolumn electron-beam direct write lithography system, namely Multicolumn Electron-Beam Lithography. Its equipment has entered SkyWater's production facility in Minnesota for rapid prototyping, special chip manufacturing, Secure Chip ID and large-area device patterning.

In 2025, the company completed a 31 million U.S. dollar Series B financing, with investors including: Onto Innovation, Lam Capital, UMC Capital, MediaTek Capital. It can be seen that these investors cover metrology and inspection, etching equipment, wafer foundry and chip design, indicating that Multibeam has been recognized by the industrial chain to a certain extent.

The up to 140 million U.S. dollars obtained by Multibeam this time will be used to develop multi-chip assembly, stacking and high-density interconnection technologies. The company's core capability is multi-electron beam direct writing, which does not fully rely on traditional photomasks, but uses multiple micro electron beam columns to directly complete high-precision patterning. Multibeam claims that its solution can support full-wafer level interposers, adapt to chiplet offset, and reduce transmission energy consumption by shortening the inter-chip connection lines.

Thintronics is an electronic material startup in California, developing ultra-low loss dielectric materials for chip packaging substrates, PCBs and interposers. The up to 50 million U.S. dollars obtained by Thintronics will be used to develop ultra-low loss interlayer dielectrics. Dielectric materials directly affect the loss of high-speed signals in packaging substrates, interposers and PCBs.

After the rate evolves from 112G to 224G and even 448G, the dielectric constant, loss factor, thickness uniformity and thermal stability of materials may all determine whether the system can operate reliably. Thintronics claims that its substrate dielectric can improve insertion loss by 30% to 50% under 224G and 448G PAM4 conditions, and hopes to make the same low-loss dielectric cover PCBs, packaging substrates and interposers.

Extropic: A new computing paradigm

Among the seven projects, Extropic is the most experimental one.

The U.S. Department of Commerce plans to provide it with up to 75 million U.S. dollars to develop the thermodynamic sampling unit TSU. Unlike CPUs and GPUs that execute deterministic instructions, TSU uses the natural thermal fluctuations in electronic circuits to directly generate samples from programmable probability distributions.

Extropic's judgment is that generative AI essentially contains a large number of probability sampling tasks, but current computers usually first perform large-scale matrix operations to calculate the probability distribution, and then sample from it. TSU tries to complete the sampling process directly, reducing the data communication and matrix calculation of traditional digital circuits.

The company has manufactured the X0 chip for technical verification, and launched an experimental platform including CPU, FPGA and TSU daughter boards. It claims that local communication and probabilistic circuits can significantly reduce the energy consumption of some sampling tasks.

But this does not mean that TSU can directly replace GPUs. It is more like a dedicated accelerator for probabilistic models, optimization, simulation and generation tasks. How algorithms are mapped to TSU, whether the software ecosystem is mature, whether the accuracy is controllable, and how much workload it can undertake in real large models all need further verification.

OBSIDIA: Introducing hardware-level anti-counterfeiting

Among the seven companies, OBSIDIA receives the least amount of funding, up to 34 million U.S. dollars. OBSIDIA Semiconductors was founded in 2025, and it is also one of the youngest enterprises among the seven.

Public data from SEMI shows that the company CEO Erik Hosler has participated in advanced lithography and semiconductor technology startups, and founded OBSIDIA in 2025, aiming to realize the authenticity and integrity verification of chips from wafers to end systems.

The company's public team size is very small, and the content disclosed on its official website is also very limited. Its public introduction positions the product as "Hardware Zero-Trust".

OBSIDIA claims that its Silicon Blockchain Identity can establish identity information for chips without increasing the wafer manufacturing steps and cycle costs, and verify the authenticity and integrity during the supply chain and operation process.

The company also disclosed that its first set of REELScan test systems has been installed on the ParPro Technologies production line, used for verification before electronic components enter the SMT assembly process, and plans to deploy more test equipment to a small number of customers in 2026.

NIST stated that the up to 34 million U.S. dollars that OBSIDIA intends to obtain is mainly used to develop non-intrusive counterfeit chip and malicious component identification systems to ensure source verification and traceability of AI and advanced electronic supply chains.

From subsidizing wafer fabs to investing in technology portfolios

Compared with the early days of the CHIPS and Science Act, when hundreds of billions of dollars were poured into the manufacturing side all at once, the way the CHIPS Act funds are used is now undergoing two major changes.

The first change is shifting from supplementing manufacturing capabilities to selecting technical routes.

CPO, ferroelectric memory, electron beam direct writing, and thermodynamic computing are all mature projects that have not yet formed stable commercial returns. Government funds no longer only undertake the cost of enterprise plant construction, but the risk of technologies moving from the laboratory to engineering and mass production.

The second change is shifting from free incentives to equity investment.

All seven companies this time are required to provide the U.S. government with a minority stake without control rights. This is not an isolated arrangement. The 2 billion U.S. dollar quantum computing portfolio announced in May 2026 also requires minority stakes in funded enterprises; when the U.S. Department of Commerce provided 250 million U.S. dollars of silicon carbide R&D funds to I-Pulse in June, it also obtained a minority stake.

Looking back at the CHIPS and Science Act passed in 2022, the core fund pool led by the U.S. Department of Commerce is divided into two parts: 39 billion U.S. dollars in manufacturing incentives and 11 billion U.S. dollars in R&D investment. The early policy focus was mainly on wafer fabs, equipment and basic manufacturing capabilities, and its strategic appeal was "reshoring production capacity", attracting giants such as TSMC, Samsung, Intel, and Micron to build factories in the United States with huge investments.

The 874 million U.S. dollar letter of intent announced this time only uses a tiny fraction of the 11 billion U.S. dollar R&D fund. The U.S. Department of Commerce and Natcast (the operating entity of the National Semiconductor Technology Center NSTC) have clearly stated in their follow-up plans: they will, in the form of a national fund, continuously search for and heavily support cutting-edge projects and startup unicorns that can subvert the existing semiconductor paradigm in the long term.

It can be seen that the logic of this set of combined punches by the United States has been completely unblocked: large wafer fabs such as TSMC, Intel and Samsung are responsible for solving the computing power capacity anxiety in the next 3-5 years; while this batch of CPO, thermodynamics, ferroelectric memory startups that have been taken equity stakes by capital are the seed players for the United States to lock in the rule-making power of the "post-Moore's Law era" in 5-10 years.

A larger-scale, deeper-penetration "post-GPU era betting matrix" backed by national will has been laid out secretly. In this top-level game related to the polar axis of computing power in the next three decades, there will inevitably be more hidden hard technology unicorns that will be forcibly included by the U.S. government in the attitude of a "national-level VC", becoming new chips for it to reshape the global hard technology landscape.

This article is from the WeChat official account "Semiconductor Industry Observer" (ID: icbank), author: Du Qin DQ, and is published with authorization from 36Kr.