Self-developed high-performance distributed solution, Xinxiao Technology shortens the chip power sign-off cycle from several weeks to just a few days | Underwater Project

An advanced process chip needs to go through hundreds of links from design, verification to tape-out and manufacturing. Among them, Power Sign-off is the final and most critical step in the design process, which is equivalent to the completion acceptance of the entire building's power supply system when constructing a high-rise building.

Specifically, power sign-off conducts a holistic analysis of hundreds of millions of nodes on the power network to test the power consumption, voltage drop, electromigration and other performance of the power supply network, so as to determine whether the chip can smoothly enter mass production and tape-out. Once the result goes wrong, it will not only lead to substandard chip performance, but even cause tape-out failure.

Since the chip power network is an interconnected structure composed of a large number of metal wires, it must be analyzed as a whole during power sign-off. "It is equivalent to solving a sparse matrix equation with dimensions as high as hundreds of millions, and it takes a lot of time to complete one run." explained Xie Zhuo, General Manager of Xinxiao Technology.

As the chip process node continues to shrink and the number of transistors increases exponentially, the power sign-off cycle is further extended, and a complete power sign-off often takes several weeks. If the analysis result is not ideal, design engineers also need to modify the layout according to the feedback and then repeat a round of power sign-off.

In response to this industry pain point, Xinxiao Technology adopts distributed matrix solving technology to break the bottleneck that power sign-off efficiency restricts chip delivery cycles. The company's first digital power sign-off tool "IcPower" supports advanced processes such as 7nm, can meet the power supply requirements of tens of billions of gate-level chips, and is 4.5-8.5 times faster than tools from leading overseas manufacturers in typical test cases. It has been put into use in the chip design links of many domestic chip manufacturers.

1. Adopting Distributed Solving Technology to Improve Power Sign-off Efficiency by 3-10 Times

Before founding Xinxiao Technology, Xie Zhuo once served as the head of the Chinese technical team for Voltus, a power integrity analysis tool of the world-renowned EDA manufacturer Cadence.

According to his introduction, the core technical idea of distributed solving comes from the "domain decomposition method" in the field of computational mathematics. By splitting the huge matrix of power sign-off into many small matrices that can be calculated efficiently, and using multiple computers for parallel computing, the overall solving time is shortened. Each analysis tool will adopt a similar method when solving large-scale problems, but the difficulty lies in the uneven solving efficiency of different tools.

Xie Zhuo said that the difficulties are concentrated in both algorithm and engineering aspects.

The first is to split "scientifically", that is, targeting the characteristics of the sparse matrix of the power network, adopting an intelligent domain decomposition algorithm based on graph theory to scientifically split the tens of billions of level global matrix into multiple sub-matrices, and minimize the boundary coupling between sub-matrices.

The second is to use a distributed matrix solver to optimize the communication topology and message transmission mechanism between nodes, which greatly reduces the network communication overhead in the distributed environment. In the process of distributed split solving, it is also necessary to introduce a strict numerical stability control algorithm to ensure that the results of distributed computing and the high-precision solver on a single machine are strictly consistent in the mathematical sense, so as to meet the strict sign-off accuracy requirements of advanced processes.

Relying on the team's technical accumulation and innovation at the algorithm and engineering levels, Xinxiao Technology enables IcPower to achieve a 3-5 times speed increase compared with overseas tools. "For some dynamic analyses that take an extremely long time, the speed of some test scenarios can be increased by more than 10 times. The power sign-off that used to take several weeks to run can be completed by IcPower in just a few days." Xie Zhuo said.

IcPower Measured Performance Comparison

2. Seize the Domestic Substitution Dividend and Commit to Building a Chip Design Platform

Like many EDA tool start-ups that have emerged in recent years, Xinxiao Technology entered the power sign-off track to seize the current window period of "domestic substitution" in the EDA industry.

The global EDA market has long been monopolized by three giants: Synopsys, Cadence and Siemens EDA. A report from China Galaxy Securities shows that the three companies account for about 74% of the global market share. The escalating Sino-US technology game in recent years has prompted more and more domestic chip companies to attach importance to using domestic tools as alternative or backup solutions.

Based on confidence in product performance, Xinxiao Technology chooses to benchmark against overseas tools in its business model, focusing on software licensing with pricing comparable to that of overseas tools. At present, IcPower has been put into use in many domestic chip design companies, covering domestic CPUs, GPUs, intelligent driving chips and other types of chips, and is continuously iterating its product performance with the help of customers' extensive design cases and test platforms in the application process.

Xie Zhuo revealed that Xinxiao Technology's revenue reached several million yuan in 2025. "The R&D cost of software is basically fixed, and the more customers we have, the stronger the profitability will be."

But he also admitted that expanding customers is the current difficulty in commercialization. "Customers often worry that start-ups cannot guarantee the sustainability of product supply, so they prefer to choose larger-scale enterprises, although large companies may not be as capable of innovation as start-ups."

In the second half of 2026, Xinxiao Technology plans to launch a new round of financing after the angel round, focusing on introducing capital from industrial parties, in order to get more support in market expansion.

Represented by the "Tao (τ) Law" proposed by Huawei, as Moore's Law is gradually approaching the physical limit, the chip industry is shifting from process shrinking to vertical stacking, which means that the analysis scale of power sign-off will grow exponentially.

"The stronger the underlying technology accumulation, the more competitive you will be in this direction." Xie Zhuo said that Xinxiao Technology's product roadmap will also be developed around this trend. In the second half of the year, the company will launch thermal analysis and stress analysis products to support complete thermo-mechanical coupling analysis, helping customers identify heat generation and thermal stress problems caused by chip stacking in the early stage of 3DIC design.

In addition, Xinxiao Technology is also exploring the application of AI agents in chip design, enabling customers to call tools and complete various design tasks through natural language, and finally build an AI-driven chip design platform that can access other EDA tools.

Whether this path planned by Xinxiao Technology can be successfully realized depends not only on whether the core technology can be verified in more scenarios, but also on the large-scale procurement willingness of customers in the future and the continued confidence of the capital market in the company's development potential.