AMD challenges NVIDIA's full-stack barriers, get a full insight into AMD AAI 2026 through this article

On July 24, AMD launched the Helios rack-scale AI platform and the 6th-gen EPYC "Venice" server CPU at the Advancing AI 2026 event. Helios integrates the next-generation Instinct MI455X GPU, Venice CPU, and Pensando networking system. AMD also unveiled the MI430X for scientific computing, the PCIe-form-factor MI350P, ROCm.AI, as well as the "Gorgon Halo" and Kria AI Robotics developer platforms designed for local Agents and robotics.

Lisa Su set a clear narrative thread for this launch: AI computing is shifting from training acceleration to inference, and Agents have extended a single model call into continuous inference, tool invocation, and task execution. AMD estimates that approximately 60% of global AI computing power will be dedicated to inference by 2026. She noted that Agents require both "massive GPUs to handle inference" and "massive CPUs to orchestrate every step."

In response to this shift, AMD has summarized its strategy as computing leadership, open platforms, and "making AI ubiquitous." Helios stands at the core of this strategy: AMD aims to integrate GPUs, CPUs, networking, and software into a complete AI factory platform, elevating competition from individual chips to rack throughput, Token cost, and system delivery.

01 MI455X and Helios: Competition Shifts to the System Level

The MI455X and Helios are the focal points of this launch.

The MI455X is equipped with 432GB of HBM4, delivering a memory bandwidth of 23.3TB/s, a peak MXFP8 computing performance of 20PFLOPS, and a peak MXFP4 computing performance of 40PFLOPS. Compared to the previous-generation MI355X, its memory capacity has increased by up to 1.5x, memory bandwidth by up to 2.9x, and low-precision peak computing performance by up to 4x.

Memory is the key focus of this generation's upgrade. As model parameters expand and context length grows, inference requires long-term storage of more weights and KV Cache. The MI455X's simultaneous upgrades to computation, cache, memory, and interconnectivity ultimately target higher real-world workload efficiency.

AMD also provided a generational comparison of the MI455X in DeepSeek V4 Flash FP4 inference. Under pre-production or reference hardware conditions with specific models and configurations, the MI455X achieves up to 34x the Token throughput of the MI355X and reduces Token costs by up to 18x. This improvement stems from multiple factors including hardware, low-precision computing, and software optimizations, and still requires validation from mass-produced products.

Beyond individual GPUs, Helios carries a more significant strategic mission.

In Lisa Su's view, cutting-edge AI can no longer be satisfied by a single chip or a single server, and "the entire rack must be designed as one unified system". CPUs handle scheduling and execution, GPUs perform model computations, high-speed networks connect the inside and outside of the rack, and software determines whether this hardware stack can be rapidly deployed and continuously optimized. Helios is AMD's direct response to this paradigm shift.

Traditional 72-GPU clusters typically consist of 8-GPU servers connected via scale-out networks. Each server has independent memory, and inter-GPU communication requires multiple network hops, which easily introduces latency, congestion, and data locality constraints.

Helios organizes 72 MI455X GPUs into a unified rack-scale system, providing approximately 31TB of HBM4 and 260TB/s of aggregated scale-up bandwidth. AMD summarizes this transformation as "the rack becomes the new system."

The full Helios system comprises 18 compute trays and 6 switch trays, using the UALoE Scale-up Fabric to connect all 72 GPUs within a single compute domain, enabling single-hop interconnectivity inside the rack. Every GPU has consistent bandwidth access to all other GPUs, reducing the need for software to adapt to complex network topologies and data locality constraints. The system adopts a multi-plane fabric with redundant paths: in the event of a link or switch node failure, traffic can be rerouted to available paths, isolating faults to local segments.

This architecture also means AMD has to strike a balance between GPU density and host CPU capabilities. Each Helios compute tray uses a configuration of "1 CPU + 4 GPUs."

When pressed by media on-site about whether this ratio is primarily designed to cut costs and whether the CPU would become a system bottleneck, AMD responded that its goal is to pack as many GPUs as possible into a single rack. The core count, memory capacity, and I/O capabilities of a single Venice CPU are fully sufficient to support 4 GPUs, making the 1:4 ratio the optimal balance under current design constraints. Whether this ratio can maintain sufficient headroom when running Agent and complex inference workloads still requires further validation through customer deployments.

Helios's system engineering extends to power delivery, liquid cooling, cabling, and maintenance. Official documentation states that the full rack power consumption ranges from 225kW to 245kW, depending on workloads. The compute trays, switch trays, and cooling manifolds all use modular designs, allowing partial maintenance inside the rack to minimize full disassembly and downtime.

However, modularity currently primarily addresses service and repair issues. When further asked by media whether Helios can support continuous future upgrades, allowing CPUs, GPUs, and networking components to be directly replaced as products iterate, AMD did not make explicit cross-generation compatibility commitments. It only noted that the current system has been designed for modularity and maintainability, and future iterations will continue to improve upgrade and service capabilities. This means whether Helios can evolve from a modular rack into a platform that protects customers' long-term hardware investments will depend on the interface and architecture design of the upcoming MI500 and subsequent systems.

Lisa Su repeatedly emphasized in her keynote that customers ultimately care about how many users and how many Tokens each unit of investment can generate. As inference budgets continue to grow, peak computing performance must be translated into higher throughput under fixed power consumption and lower per-Token costs.

In modeling based on Kimi K2 Thinking, estimated system pricing, and different interactivity intervals, Helios delivers up to 30% higher Token output per dollar than NVIDIA's Vera Rubin NVL72. Under specific interactivity conditions, single-GPU Token throughput is approximately 10% to 15% higher. These results are based on pre-production systems and price assumptions; the performance, pricing, and operating costs of mass-produced units will ultimately determine whether Helios can deliver on its system-level advantages.

Figure: Helios Demo showcased at AMD Advancing AI 2026

AMD has designed a three-layer networking architecture for Helios: the Salina DPU handles front-end networking, storage, and security offloading, UALoE manages scale-up interconnectivity for the 72 GPUs inside the rack, and the Vulcano AI NIC supports scale-out expansion across multiple Helios racks. These three components cover the data paths at the server ingress, within the rack, and across multi-rack clusters respectively.

UALoE connects 72 GPUs and approximately 31TB of HBM4 within the same fabric, delivering 260TB/s of aggregated bandwidth. Vulcano supports 800G and PCIe 6.0, providing each GPU with up to 2.4Tbps of scale-out bandwidth. Salina reduces CPU overhead on networking, storage, and security tasks via hardware offloading, while adding KV Cache expansion capabilities optimized for long-context workloads.

With these three networking layers integrated into Helios, Pensando has evolved from an independent cloud infrastructure business to a core component of AMD's AI platform.

02 Venice: EPYC Expands from Traditional Servers to Agent Workflows

Following the Helios announcement, AMD dedicated significant presentation time to its server CPUs. Based on Lisa Su's assessment, the incremental computing demands brought by Agents do not fall solely on GPUs. A single Agent task also needs to execute code, query databases, invoke tools, and coordinate numerous parallel steps, creating a new category of server workloads. She predicts that as the number of Agents scales from millions to billions, the server CPU market will expand significantly.

AMD simultaneously launched its 6th-generation EPYC 9006 series server CPUs, codenamed Venice, targeting cloud computing, enterprise data centers, and AI use cases. The company positions this lineup as a portfolio of CPU products designed to address diverse requirements across modern data centers, rather than a single flagship model.

The Venice product family includes four primary lines:

EPYC 9006 SP7 "Venice" focuses on high core counts and top-tier performance; EPYC 9006 SP8 "Venice" prioritizes system cost-effectiveness for enterprise scenarios; EPYC 9006X SP7 "Venice-X" targets HPC and AI data preprocessing; and EPYC 9006 LP "Verano" uses LPDDR memory for high-performance AI host nodes.

Venice delivers up to 256 cores and 512 threads, built on the Zen 6 architecture, with support for PCIe 6.0 and various DDR5, MRDIMM, and LPDDR configurations. This full spectrum of options covers general-purpose computing, enterprise applications, HPC, GPU hosting, and AI preprocessing.

In the era of Agentic AI, a complete Agent workflow includes gateway processing, context assembly, planning, retrieval, tool execution, validation, and output, with most of these steps running on CPUs. As multiple Agents execute in parallel, CPU core density, memory bandwidth, virtualization, and I/O capabilities directly impact task scheduling and sandbox concurrency.

Server CPUs are a business where AMD has already made significant inroads. Official materials show that EPYC server CPUs have reached a 46% revenue share, with AMD noting that one Fortune Global 2000 enterprise switches to AMD every week. To date, there are over 475 EPYC platforms and more than 1600 EPYC cloud instances available globally.

Venice faces competition on two fronts: from Intel Xeon, where AMD aims to continue expanding market share by leveraging core density, performance-per-watt, and server consolidation capabilities, and from NVIDIA's Vera paired with Arm server CPUs, as CPU competition becomes increasingly intertwined with GPU platforms and system architectures.

03 ROCm.AI: AMD Leverages AI to Lower Barriers for GPU Software Development

Software is a key new highlight of this launch event.

AMD officially introduced ROCm.AI, positioning it as an AI-driven platform for developers. Building on AMD's existing foundational ROCm software stack, ROCm.AI adds AI-assisted capabilities for GPU code generation, migration, debugging, and performance optimization, and supports integration with tools and models including Cursor, Claude, Codex, and Gemini.

The core objective of ROCm.AI is to reduce the complexity of low-level GPU programming and CUDA migration. Developers can use AI to analyze code, convert between CUDA and HIP implementations, identify performance bottlenecks, and generate optimization recommendations.

AMD also highlighted FlyDSL, a Pythonic domain-specific language that allows Python developers to focus more on algorithm expression while reducing the overhead of GPU orchestration tasks such as thread management, memory handling, and low-level scheduling. AMD claims that in relevant examples, FlyDSL achieves equivalent or better performance with lower development complexity.

ROCm.AI is scheduled to be available in August 2026. AMD disclosed that over 3 million models on Hugging Face can run out-of-the-box on AMD platforms, the top 10 open-source AI projects have native AMD support, and the number of related open-source contributions has increased more than 10x.

These metrics demonstrate the rapid expansion of the ROCm ecosystem, but the true competitiveness of the software platform will ultimately depend on model adaptation speed, operator performance, migration costs, and production environment stability. For AMD, the significance of ROCm.AI lies in advancing software support from low-level compatibility to a superior developer experience.

04 Local Agents: Extending Inference from the Cloud to Personal Devices

On the client side, AMD did not launch new Ryzen processors this time. Instead, it demonstrated local AI inference capabilities, software ecosystems, and enterprise-grade Agent solutions centered on its existing Ryzen AI 400, Ryzen AI MAX, and the Ryzen AI Halo developer platform built on top of Ryzen AI MAX.

AMD attributes the push for local AI acceleration to three key requirements: eliminating the need to send data to third-party processors, reducing the continuous Token costs generated by high-frequency inference, and maintaining functionality even when disconnected from networks. At the same time, the capabilities and efficiency of small models continue to improve steadily.

In terms of hardware capabilities, Ryzen AI 400 is optimized for models up to approximately 24B parameters, while Ryzen AI MAX supports much larger local models. The Ryzen AI Halo developer platform is equipped with up to 128GB of unified memory, with AMD targeting native execution of models with up to approximately 200B parameters.

AMD also previewed a follow-up platform codenamed "Gorgon Halo," which will increase unified memory to 192GB, expanding the maximum supported local model size to around 300B parameters.

Enterprise-grade Agents are another key priority for AMD to drive local AI deployment. AMD jointly demonstrated a full-stack edge solution with Cisco, integrating Ryzen AI Halo hardware, Lemonade local inference, model routing, and Agent sandboxes with Cisco's networking, security, policy control, and observability capabilities. Enterprises can use this solution to restrict Agent access scopes, enforce unified security policies, and continuously track inference costs, Token efficiency, and real-world usage patterns.

From this perspective, AMD aims to upgrade personal devices from interactive terminals that only call cloud AI to compute nodes capable of running local models, executing Agents, and being governed under unified enterprise management. The cloud will continue to handle larger-scale, more complex tasks, while local devices will take on workloads with higher requirements for privacy protection, cost efficiency, response speed, and offline availability.

05 Physical AI: Chips, Modules, Software, and Ecosystem Deploy Simultaneously

The Physical AI segment includes five distinct launches, covering multiple layers of robotics computing from chips to full ecosystem.

The first launch is the Ryzen AI Embedded X100 series, which integrates CPU, GPU, and NPU on a single platform for robot perception, inference, planning, and control, and is currently in the sampling phase.

The second launch is the Kria AI System-on-Module based on the X100 series. This module adopts the 120×120mm COM-HPC open standard form factor, integrates CPU, GPU, NPU, and unified memory, and is designed for mass-produced robots. AMD's listed test examples include VLA inference latency under 100ms, real-time control loops of 125 microseconds, and visual classification latency below 0.4ms. Some of these results come from partner testing and cannot be directly extrapolated to other workloads.

The third launch is the Kria AI Robotics Developer Platform, which AMD calls "the industry's first open, turnkey, all-in-one robotics development platform" designed to integrate compute hardware, sensors, software, and reference systems, with availability scheduled for the fourth quarter of 2026.

The fourth launch is the AMD Robotics Software Suite, which includes the Robotics Core SDK, Physical AI SDK, accelerated ROS nodes, MoveIt 2, and optimized modules for audio and manipulation. Built on ROCm and HIP, it emphasizes using a unified AI software stack from the cloud to edge robots, and is currently in the Early Access stage.

The fifth launch is the AMD Robotics Partner Network, which includes more than 30 initial partners spanning robot OEMs and ODMs, AI models, sensors, middleware, simulation, digital twins, and system integration.

With these offerings, AMD has