Semiconductor equipment, a new track is gaining traction
From 2025 to 2026, a new trend emerged in the semiconductor equipment industry. A group of semiconductor equipment manufacturers are intensively launching new equipment for square substrates. From lithography, metrology, CMP, photoresist stripping, electroplating to laser via holes, slot coating, and glass metallization, "Panel Level Packaging (PLP)" is forming a new niche track on the equipment side. And this time, domestic equipment manufacturers are not absent.
01 Advanced Packaging Starts to "Change from Circle to Square"
A report released by SEMI shows that in the first quarter of 2026, the global semiconductor equipment shipment value increased by 14% year-on-year, reaching $36.55 billion, and increased by 1% quarter-on-quarter. The record quarterly sales were driven by continuous AI-related investments, including capacity expansion and technological upgrades to support advanced logic chips, DRAM, and advanced packaging.
CoWoS (Chip-on-Wafer-on-Substrate) is the current mainstream solution for high-end chip packaging in global AI/HPC. In 2025, CoWoS occupied 69% of the market share of 2.5D/3D advanced packaging technologies. This technology is a 2.5D advanced packaging technology developed and dominated by TSMC. It was announced for R & D in 2011. Its core is to integrate heterogeneous chips such as logic chips and high-bandwidth memory (HBM) through a silicon interposer, and then interconnect with an organic substrate to achieve high-density, high-performance system-level integration, which can effectively improve bandwidth, reduce power consumption and latency. CoWoS is currently mainly used in fields such as artificial intelligence (AI), high-performance computing (HPC), and data centers. Many high-end AI chips of companies such as NVIDIA, AMD, and Google widely adopt this technology.
In addition, as AI chips are getting larger and more complex in design, the area utilization and packaging efficiency of traditional circular wafers are gradually limited. Therefore, it starts to "replace circles with squares", replacing wafers with panels, arranging chips on a rectangular substrate, and finally connecting them to the underlying carrier board through the packaging process, so that multiple chips can be packaged together, which is CoPoS (Chip-on-Panel-on-Substrate).
The most core technical advantage of panel-level packaging lies in replacing circular wafers with square panels, thus greatly improving material utilization. Taking a standard 610mm × 457mm printed circuit board as an example, its area is about 4 times that of a 300mm wafer. Theoretically, the number of packages that can be manufactured in a single batch is 4 times that of wafer-level packaging. In addition, since the chips themselves are square, arranging them on a rectangular panel substrate further optimizes space utilization compared to the edge waste of circular wafers.
The semiconductor industry follows the law of "one generation of materials, one generation of processes, one generation of equipment". As advanced packaging "replaces circles with squares", the pre - layout of equipment manufacturers has been fully launched.
02 International Giants Layout Panel-Level Packaging
Panel-level packaging requires processes such as substrate preparation, photoresist coating, exposure/lithography, development, descum, seed layer deposition, electroplating, CMP planarization, TGV via holes, via metallization, and metrology inspection. Its process chain seems similar to wafer-level packaging (WLP), but in fact, each step is different. To match larger warpage, larger area, and larger material deformation, almost every type of equipment for panel-level packaging needs to be redesigned from coating to inspection.
On this process chain, international giants have taken the lead in seizing positions. Relying on their technological accumulation in the wafer-level equipment field, international giants are laying out the full-chain process and building ecological barriers.
Lithography and Metrology: Onto Innovation's JetStep S3500 lithography system is specially designed for panel-level advanced packaging production. This system can handle chip offsets caused by placement accuracy errors, CTE (coefficient of thermal expansion) mismatch, and panel warpage. It has a large exposure field (59.4 × 59.4 mm), a resolution of up to 2/2 μm line width/line spacing (L/S), and can be optionally upgraded to a resolution of 1/1 μm. In addition, the system supports multiple exposure wavelengths and is very suitable for process development using new photosensitive polymers. Options for specific applications include warped panel handling, real-time optical focusing, and chip offset correction to ensure the accuracy and reliability of panel-level packaging. Manufacturers such as ASML, Nikon, Canon, Ushio, and SCREEN are also laying out related products.
RDL Equipment: Manz successfully delivered the world's first 310mm × 310mm panel-level packaging (PLP) electrochemical deposition (ECD) mass production equipment. The new ECD platform can flexibly support glass and metal square carriers and integrates key wet process technologies for the redistribution layer (RDL), providing mass production solutions for advanced packaging architectures such as FOPLP, CoPoS, and TGV. Centered on the ECD equipment, Manz also further integrated key wet process equipment such as cleaning, development, etching, and film stripping in this machine delivery, and supports both spin and spray process modes, forming a complete panel-level RDL process solution, Omni 310x. Omni 310x (310mm × 310mm) has officially joined the existing Omni 510x (510mm × 515mm) and Omni 700x (700mm × 700mm) series, forming a complete panel-level mass production platform layout. Through the modular design architecture and flexible automation integration capabilities, it can be customized according to the product architectures, packaging technologies, and capacity requirements of different customers, providing a more flexible technical path to support the needs of various stages from R & D verification, trial mass production to large-scale production.
Laser Via Holes: Trumpf Group in Germany and SCHMID Group in Germany have jointly developed a "laser etching + wet chemical treatment" process. This process first uses Trumpf's TruMicro series of ultra-short pulse lasers and the TOP Cleave laser focusing head dedicated to glass processing to selectively modify the glass; then uses an etching solution to etch away the laser-modified areas to generate the required high-precision via holes.
In addition, leading front-end equipment manufacturers such as Applied Materials, Lam Research, TEL, and KLA have all included panel-level packaging in their advanced packaging strategies.
03 Domestic Equipment Manufacturers Intensively "Submit Their Papers"
While international giants are building ecological barriers, domestic equipment manufacturers are not absent either, seizing the entry tickets for the new track. From 2025 to 2026, domestic equipment manufacturers are moving from "verification" to "shipment" at the key process nodes of panel-level packaging.
Huahai Qingke Secures the First Domestic Mass Production Order
In panel-level packaging, the CMP process directly determines the flatness, defect level, and interface quality of the dielectric layer and metal layer, and is the core link to ensure the interconnection reliability and the final chip performance and yield. The first domestic fully automatic board-level CMP mass production equipment, Master-P510APEX, independently developed by Huahai Qingke, has successfully obtained an order from an important customer in the advanced packaging field and will be put into mass production on the customer's production line as planned. This marks a key breakthrough of domestic high-end equipment in the core process of advanced packaging and is also an important milestone for Huahai Qingke's CMP equipment technology to extend from the wafer level to the board level.
Northern Huachuang Releases Special Process Equipment for Board-Level Packaging, and the First Panel-Level Packaging Descum Equipment Leaves the Factory
In the semiconductor manufacturing process, the Descum process is an important link affecting product yield and production efficiency. Recently, Northern Huachuang's first 600mm×600mm panel-level packaging descum equipment successfully left the factory.
Its board-level packaging descum equipment is mainly used for dry processes such as plasma descum, residue removal, surface modification, and treatment in the field of board-level packaging, and can handle substrates with a maximum size of 600mm×600mm. For high-temperature sensitive materials such as PI, PR, and ABF, the board-level packaging descum equipment is equipped with an active cooling system, which can stably control the substrate temperature within 75°C, greatly improving the yield. Based on the dynamic electrode spacing adjustment technology, the equipment can optimize the plasma distribution state in real-time according to the different process requirements of materials such as PI, PR, and ABF. This not only makes the descum effect highly uniform on the large board surface, widening the process window; at the same time, it significantly shortens the single-batch process time, making the unit output higher.
In addition to the descum equipment, the board-level packaging PVD equipment released by Northern Huachuang in March this year is specially used for TGV and RDL processes in the field of board-level packaging, supporting the deposition of metals such as adhesion layers and seed layers, and can handle substrates with a maximum size of 600mm×600mm. The board-level packaging PVD equipment adopts the large-capacity cluster-type cluster architecture independently designed by Northern Huachuang Vacuum. Based on the mature large-warpage substrate transfer system control, it can mount up to 10 chambers at the same time, significantly optimizing the space occupation while achieving high integration. For different process routes, the equipment can flexibly mount various chambers such as PVD, Degas, Preclean, Flipper, and Cooling to meet diverse coating requirements. The excellent magnetic field control scheme can achieve ultra-high target utilization, effectively reducing consumable costs, and at the same time, the high deposition efficiency greatly improves the capacity of a single device.
The board-level packaging PIQ equipment released at the same time is developed based on wafer-level PIQ technology and is mainly used for the PI photoresist curing process in the field of board-level packaging, and can handle substrates with a maximum size of 510mm×515mm. The board-level packaging PIQ equipment uses vertical large-diameter furnace body heating technology, which can control the temperature uniformity within ±3°C, ensuring the PI curing quality from the source. The independently developed oxygen control and particle technology can quickly control the oxygen content in the process chamber and the loading area to below 10ppm, and the particle control reaches the wafer level. While effectively preventing PI oxidation and ensuring the film layer performance, it provides more possibilities for exploring fine packaging processes with smaller line widths.
ACM Research Seizes Positions in Wet Processes and Electroplating
Electroplating equipment is used in processes such as RDL (redistribution layer) manufacturing and TSV (through-silicon via) filling in advanced packaging. In 2025, ACM Research delivered the first horizontal panel electroplating equipment, Ultra ECP ap-p, to a panel manufacturing customer. This system uses the horizontal electroplating technology protected by ACM's patent application and supports electroplating processes for multiple materials such as copper, nickel, tin-silver, and gold. Among them, the copper electroplating chamber is equipped with a high-speed electroplating paddle designed for high bump applications, which can achieve a bump height of more than 300 microns. The Ultra ECP ap-p equipment uses a four-sided sealed dry contact chuck to improve reliability, is equipped with an in-chamber cleaning function to minimize chemical cross-contamination between different electroplating chambers, and adopts a horizontal electroplating design - achieving excellent film thickness uniformity through a synchronous rotating chuck and a rotating rectangular electric field.
It also obtained an order for a panel-level advanced packaging negative pressure cleaning equipment from a global leading semiconductor packaging manufacturer outside the Chinese mainland and delivered it in the first quarter of 2026. The panel-level advanced packaging equipment order obtained this time is the Ultra C vac-p panel-level negative pressure cleaning equipment independently developed by ACM Research (under global patent application protection), which is specially designed to meet the strict process requirements brought by advanced fan-out panel-level packaging (FOPLP) and fine-pitch interconnection. This equipment improves the impurity cleaning efficiency and process uniformity through the liquid penetration ability in a vacuum environment, ensuring the yield and reliability of complex 2.5D and 3D integration solutions. The equipment supports panel specifications of 310x310 mm, 510×515 mm, 600×600 mm, etc., and can meet the large-scale mass production needs of next-generation device architectures.
Han's Semiconductor and Dier Laser Layout Laser Via TGV Equipment
Glass substrates are regarded as the core carriers for next-generation AI packaging by giants such as NVIDIA, Intel, and Samsung due to their ultra-low warpage, high insulation, and excellent thermal stability. And TGV via hole equipment is the first hurdle for the mass production of glass substrates.
The TGV glass via hole equipment developed by Han's Semiconductor is the earliest developed in China and has been stably used in TGV mass production so far. It can realize the preparation of blind holes, special-shaped holes, and conical holes of various sizes.
On May 22, 2026, Dier Laser stated that its TGV equipment used in fields such as semiconductor chip packaging and display chip packaging has completed the shipment of panel-level glass substrate via hole equipment, achieving full coverage of laser technology for wafer-level and panel-level TGV packaging.
Guihua and Baoding Jingtong Electromechanical Complete the Key Puzzle
The process chain of panel-level packaging is extremely long. In addition to processes such as exposure, PVD, and electroplating, coating and metallization are also key links determining the yield.
Guihua's slot coating equipment is specially designed for the large-area photoresist coating needs of panel-level packaging and can achieve micron-level uniform coating on ultra-large substrates, laying the foundation for the fine patterning of the subsequent RDL (redistribution layer).
Baoding Jingtong Electromechanical has directionally developed a 515×510mm glass substrate double-sided polishing copper-nickel technology, which is the core process for the metallization of large-size glass substrates for advanced packaging (2.5D/3D, Chiplet). Its core lies in realizing a copper-nickel composite metal layer on the double-sided nano-level polished glass surface simultaneously, with high adhesion, high uniformity, and low stress. It can achieve double-sided copper thickness flattening of the glass substrate, retaining a flawless and highly flat vertical via hole surface of 1:15 or more, laying a high-yield foundation for the next step of high-density wiring. Currently, this equipment has passed the assessment of glass substrate customers.
04 Why is it "Another New Track"?
The traditional advanced packaging equipment market has long been monopolized by a few international giants. However, in the field of panel-level packaging, due to the relatively new technical route and scattered customer needs, domestic equipment manufacturers have obtained a rare opportunity to start on an equal footing. More importantly, panel-level packaging is naturally related to display panel processes. TSMC and Innolux even directly purchased old LCD factories and transformed them into panel-level packaging production lines because the steps of photoresist coating, exposure, and development in the LCD process are highly similar to RDL manufacturing. This provides a springboard for a group of equipment manufacturers originally serving the display industry to cross over into the high-end semiconductor market. These factors prompt domestic equipment manufacturers to target this track and make early layouts. Although equipment manufacturers are enthusiastic, panel-level packaging is still significantly far from the stage of large-scale production.
Currently, the overall yield of panel-level packaging is still lower than that of wafer-level packaging, and the non-uniformity of panel sizes makes it difficult for equipment manufacturers to spread R & D costs through standardized mass production. More seriously, although the equipment side is progressing rapidly, materials, EDA tools, and testing standards are still relatively lagging behind. This means that the panel-level packaging equipment market will still be in the stage of small-batch verification and coexistence of multiple categories in the short term. Whoever can first establish irreplaceability at a key process node will gain an advantage in the large-scale production period.
In the past two decades, the core narrative of equipment innovation has been Moore's Law. But in the AI era, when the computing power improvement of a single chip encounters physical limits, packaging becomes the key to continuing performance growth, and panel-level packaging has become one of the optimal solutions to reduce the cost of advanced packaging and break through the capacity bottleneck. The next incremental market for semiconductor equipment may be hidden in these square panels. And this time, domestic equipment manufacturers have already obtained the entry tickets.