2nm, the ultimate battle

The semiconductor industry is entering a turning point in logic technology. Major wafer foundries are expected to showcase their 2-nanometer process technology using Gate-All-Around (GAA) Field-Effect Transistors (FETs). Three major players - Intel, Samsung Foundry, and TSMC - all plan to bring their 2-nanometer processes to the market in 2026, named Intel 18A, Samsung SF2, and TSMC N2 respectively. The launch of these technologies will redefine the competitive landscape in the fields of High-Performance Computing (HPC), Artificial Intelligence (AI) acceleration, and advanced mobile platforms.

The first chips to adopt the 2nm process will be PC and mobile System-on-Chips (SoCs), rather than (what many might think) AI accelerators or HPC devices. Most of the AI server market still relies on advanced 3nm or even 4nm processes. AMD's Venice EPYC processor is expected to be the first HPC chip to use TSMC's N2 process, with a projected release in 2026.

The Scramble Among 3.5 Giants

The race to 2nm is currently mainly a battlefield among three giants: Intel, Samsung, and TSMC. Additionally, there's Rapidus from Japan eyeing the opportunity, which we'll count as 0.5 of a giant.

First, let's look at Intel. In February this year, Intel was the first to bring its self-developed PC SoC chip, Panther Lake, to the market. The early deployment of the 18A chip doesn't indicate that Intel has a wide lead in the wafer foundry field. Instead, it demonstrates Intel's ability to integrate advanced transistor and power delivery innovation technologies into shipped products on time.

This achievement is both strategically significant and a reflection of Intel's internal strength. Intel's ability to advance its chip design reflects an improvement in its process execution capabilities. Previously, Intel's cooperation with fabless companies was limited to Microsoft - its important flagship customer - but only for small-volume products. Since the successful launch of Panther Lake, Intel has gained support from other customers, including Apple, which is undoubtedly an important testament.

Intel has made two technological leaps in its 2nm process, which is a risky move: GAA transistors and the early adoption of Backside Power Delivery (BSP) through PowerVia. Although BSP has long-term advantages in power integrity and expansion efficiency, it also represents a structural difference from traditional design methods. Adopting BSP requires a significant rearchitecture of the design, which limits the ability of customers accustomed to front-side power delivery to immediately migrate to the new system.

In contrast, competing foundries are expected to delay the implementation of BSP, likely until later in this decade, and broader industry adoption is expected around 2027. This time lag makes Intel's early deployment of BSP both an advantage and a disadvantage: it facilitates early learning and internal optimization but also raises the bar for external customers seeking near-term design migration.

Next, let's look at Samsung. They are gaining credibility through yield recovery.

Samsung has now brought its Exynos 2600 smartphone SoC using the SF2 process to the market. SF2 is not a technological leap for Samsung, as it adopted the GAA architecture as early as in its 3nm process. However, it was reported that the yield of its early GAA process was low. Although the SF2 architecture doesn't change much compared to the previous generation when compared with competitors, Samsung seems to have taken measures to address the yield issue. This is reflected in the reuse of Exynos chips in most of its Galaxy smartphones; the previous generation of Galaxy phones mainly relied on Qualcomm SoCs, indicating that Samsung has been working hard to improve the yield to support its own products, not to mention external customers. The significance of Samsung's SF2 process lies more in the commercial aspect than in the technological aspect.

Now, let's look at TSMC. They are consolidating their leading position through large-scale execution.

Everyone is eagerly awaiting TSMC's N2 process technology, the market leader. This technology is likely to be applied to Apple's iPhone before the end of the year. This will be TSMC's first application of GAA technology. Like Samsung, TSMC will not adopt BSP technology in this generation of products. TSMC's reputation is built on its ability to consistently deliver large quantities of products on time.

Although we expect this advantage to continue, it's worth noting that its most important customer, Apple, has also started collaborating with Intel. We believe this has nothing to do with Apple's concerns about TSMC's continuous supply capacity, and we expect Apple to continue to rely heavily on TSMC's production capacity. More precisely, it's the result of a combination of "capacity crunch," long lead times for cutting-edge manufacturing processes, and geopolitical factors, as the current US government is promoting the reshoring of manufacturing to the US.

Now, let's look at the emerging competitor, Rapidus.

In 2027, another new wafer foundry, Rapidus, will enter the Artificial Intelligence (AI) and High-Performance Computing (HPC) markets with its 2HP process technology. Its development plan for the HPC business may be very similar to that of other major players. However, Rapidus may have less experience in manufacturing processes than other companies. Whether Rapidus can achieve competitive yields and large-scale ecosystem support remains unknown, but its emergence reflects the growing pressure in geopolitics and the supply chain, prompting the diversification of advanced semiconductor manufacturing.

What Determines the Success of 2nm?

The differences between these approaches are becoming increasingly clear. Intel prioritizes architectural innovation through BSP integration; Samsung focuses on restoring manufacturing confidence after early GAA yield challenges; TSMC continues to emphasize execution stability and ecosystem scale. Meanwhile, new players like Rapidus are emerging. As a result, the competitive landscape depends not only on transistor density but also on manufacturability, customer migration paths, and supply chain resilience.

More importantly, designing, developing, and manufacturing chips at 2nm and below requires a whole new set of commercial and technological trade-offs. Every step, from architectural concept to manufacturing yield, will have a greater impact.

At such a small scale, the main goal of shrinking device features is to achieve several times the performance per watt, but it's not as simple as integrating more transistors on a silicon wafer. At this scale, a deviation of a few atoms, or a nanoscale void or burr in the signal path, can affect performance. Wires and metal layers become so thin that any anomaly can lead to unexpected thermal gradients and thermal migration, reducing reliability and shortening the device's lifespan. Additionally, materials such as photoresist require extremely high purity, with impurity levels measured in parts per quadrillion.

Complexity is exploding at all levels and can have a chain reaction in unexpected places. Multi-chip components may contain tens or even hundreds of billions of transistors, multiple types of memory, and multi-layer/multi-chip wiring and power supply schemes. Managing all these components, both locally and globally, requires multiple professional fields across traditional boundaries, and almost all aspects require multiple iterations.

From an economic perspective, almost all cutting-edge chip designs are targeted at specific suppliers or workloads. Well-funded companies can afford these expensive advanced-node chips. They hope the chips can be customized for specific data types and operating conditions and that they can leverage this customization in multiple generations of derivative chips. Meanwhile, foundries also need to be able to extend their investments beyond a single customer. The way to meet both needs is to use a common metal layer at the bottom of the chip stack (usually developed with the help of some very expensive tools and equipment) while adding more customized elements to the upper layers of the metal stack.

Almost all these cutting-edge chips are heterogeneous. Although some logic circuits use the 2nm or 18Å process, most designs also use chips developed with older processes for packaging. Hybrid manufacturing processes are not new, but the scale and potential impact of these combinations are becoming increasingly challenging. Large system companies like Google, Tesla, Microsoft, and Meta are constantly pursuing higher performance, which requires a larger area than a single photomask can provide. At least so far, the solution is to divide different functions into chip sets and connect them using an interposer, so that the logic density of each system is much higher than what a single-photomask-sized SoC can provide. However, as the number of chip sets increases, this method can easily turn from a difficult problem into an insurmountable one.

The biggest advantage of scaling to the most advanced process nodes is to reduce power consumption per square millimeter. In the past, simply scaling the process to increase the number of transistors - which was the standard method for improving performance before the FinFET era - has brought very limited performance improvements in the past five process nodes. The results vary among different foundries, but the performance improvement per node is no more than 20% (sometimes even in the single digits), and it often comes at the cost of increased power consumption. This, in turn, has led to the proliferation of 2.5D architectures (inside AI data centers), which consist of general-purpose processors and highly specialized accelerators connected through a large silicon interposer.

CPUs, GPUs, DSPs, MCUs, and FPGAs belong to general-purpose processors, while NPUs and TPUs are used to process specific data types. There are also some new types of hybrid processors on the market, such as Arm's new AGI CPU and some neuromorphic processors. However, to achieve an order-of-magnitude improvement in performance, multiple types of processors need to be combined, whether integrated on a single chip, connected within a package, installed on a circuit board, or in a rack. Moreover, regardless of the method used, a large amount of heat dissipation and device monitoring are required to ensure smooth data paths between processors and memory.

Additionally, scaling the process size below 3nm leads to an increase in gate leakage current, to the extent that FinFETs have serious leakage problems. This, in turn, increases the thermal density and exacerbates the heat dissipation problem. Currently, the solution to this problem is to use Gate-All-Around Field-Effect Transistors (also known as nanosheets), but chip manufacturers are researching complementary field-effect transistor processes, which are expected to be realized in the next few Å nodes.

In summary, the standard for measuring the transition to the 2nm process will not only be transistor density. Yield stability, ecosystem compatibility, power supply architecture, and manufacturing scale will determine which foundries can succeed in the 2nm era. As the industry transitions from the FinFET era to the GAA era, the competition is no longer about who reaches the new process node first, but about who can produce the required devices reliably on a large scale.

This article is from the WeChat official account "Semiconductor Industry Observation" (ID: icbank). Author: Editorial Department. Republished by 36Kr with permission.