Huawei proposed the Tau (τ) Law: It is biased to give it either too low or too high an evaluation.

Fast Reading

• On May 25, 2026, He Tingbo of Huawei announced the "Tao (τ) Law" at ISCAS 2026. By replacing "geometric scaling" with "temporal scaling", without relying on the most advanced lithography path, it achieves a 53.5% increase in density and a 41% increase in energy efficiency through technologies such as logic folding. In six years, 381 chip models have been mass - produced.
• This is the first time that a Chinese semiconductor enterprise has participated in the discussion of the underlying rules in the post - Moore era in a systematic way. The real value of the Tao Law lies in redefining the "mature process" as a "high - performance process", revitalizing the existing investment of tens of billions of dollars in domestic wafer fabs.
• However, the Tao Law is still before the first threshold of industry consensus. In fact, overseas giants are advancing system - level optimization in a similar direction. Treating it as a systematic project and regarding it as a long - distance race for a change of track over a decade is closer to the truth than simply shouting slogans or expecting to "subvert the global pattern in two or three years".

On May 25, 2026, the IEEE International Symposium on Circuits and Systems (ISCAS 2026) was held in Shanghai. He Tingbo, a director of Huawei and the president of the Semiconductor Business Unit, announced an industry evolution principle named in Chinese - the Tao (τ) Law in the keynote speech. This is the first time that a Chinese semiconductor enterprise has publicly and systematically proposed an evolution framework that does not rely on the most advanced lithography path to the global industry. Whether it can ultimately be accepted as a "law" by the industry community remains to be tested by time. However, the proposal of this principle itself already means that the industrial discourse of Chinese semiconductors is emerging from the single "catching - up narrative" and beginning to participate in the discussion of the underlying rules.

In the semiconductor world, Moore's Law has dominated for more than half a century. It is like an established rule, guiding the industry to make transistors smaller and pack more computing units into a unit area. However, when the size of transistors approaches the atomic level, the quantum tunneling effect leads to out - of - control leakage and heat generation. When the cost of building a 3 - nanometer production line is about $20 billion and only three or four companies in the world can afford this game, the path of geometric scaling has reached the dual ends of physical limits and business rationality. It is in this context that the proposal of the Tao Law has opened up a brand - new track for the post - Moore era.

I. What is the Tao Law: From the Space Race to the Time Revolution

The core of the Tao Law can be summarized in one sentence: Replace geometric scaling with temporal scaling.

The Chinese character "Tao" is taken from the meaning of "hiding one's light and biding one's time, and making a great effort after long - term accumulation", implying that under the pressure of external technological blockade, one should adhere to long - term accumulation and wait for the right opportunity. And τ (tau) is the time constant in circuit theory, representing the delay time for signals to propagate and switch between transistors. The smaller τ is, the faster the signal runs, and the better the response speed and energy - efficiency ratio of the chip will be.

In the past, the industry focused all its attention on how to compress the physical size (spatial dimension) of transistors to the extreme. The Tao Law turns its attention to the time of signal propagation (temporal dimension). By systematically reducing the time constant τ, it can continuously improve the transistor density and performance at the same or even more mature process nodes. This paradigm shift is essentially a reconstruction of the underlying logic of chip design. If we imagine a chip as a super - city, transistors are densely packed buildings, and electronic signals are the traffic flowing through them. The approach of Moore's Law is to make the roads narrower and build the buildings more densely, so that the vehicles travel a shorter distance. However, the roads have reached the limit. If they are made even narrower, the vehicles will either hit the wall (quantum effect) or get stuck (heat dissipation collapse). The approach of the Tao Law is: keep the road width unchanged, but build overpasses, dig underground tunnels, redesign the traffic light system, and optimize the city - wide route planning, so that the same vehicles can run faster and more smoothly on the same roads.

Specifically, the Tao Law is not a single technology but a complete system and a systematic optimization strategy that runs through four layers of coordinated optimization: devices, circuits, chips, and systems.

At the device layer, it starts from the physical foundation, optimizing the intrinsic characteristics of transistors and the parasitic resistance and capacitance of the interconnection structure, directly compressing the physical basis of the time constant τ. Without breakthroughs at this layer, all the architectural innovations at the upper layers will be castles in the air.

At the circuit layer, logic folding is the most iconic technology of the Tao Law. It folds the traditional flat - laid circuits three - dimensionally like folding paper, significantly shortening the routing length of key signal paths and allowing signals to take shortcuts in three - dimensional space instead of detours. Data disclosed by Huawei shows that the logic folding technology can achieve a step - by - step increase of 53.5% in transistor density, a 41% increase in energy efficiency, and an approximately 13% increase in the maximum frequency at the same device node. This means that applying logic folding at the 7 - nanometer process can achieve an equivalent density that exceeds the traditional 5 - nanometer level and is close to that of the first - generation 3 - nanometer flat - laid chips.

At the chip layer, it requires the collaborative design of software, hardware, and chips. Traditional chip design follows a serial model where the hardware is finalized first and then the software is adapted. However, the Tao Law requires architects, circuit designers, software engineers, and process engineers to work in parallel from the project's inception, enabling the synchronous iteration of algorithm characteristics, compiler optimization, and hardware micro - architecture.

At the system layer, it reconstructs the interconnection protocol between chips. New interconnection technologies such as Huawei's "Lingqu Bus" aim to reduce the latency of cross - chip and cross - board communication, extending the optimization from a single chip to the entire computing system.

It is worth noting that the Tao Law is not a PPT concept in the laboratory but has been verified by Huawei over a certain period of time. In the past six years, Huawei has designed and mass - produced 381 chip models (including different versions and variants) based on this paradigm, covering major product lines such as Kirin, Kunpeng, and Ascend. He Tingbo clearly revealed in her speech that the new Kirin mobile phone chip to be released in the autumn of 2026 will be the first to adopt logic folding technology. By 2031, the transistor density of high - end chips based on the Tao Law is expected to reach the equivalent level of the 1.4 - nanometer process (Huawei's planned goal). These data indicate that the Tao Law has completed the entire verification cycle from theory to product and from sample to mass production.

II. How to Apply the Tao Law: A Strategic Choice for a Long - Distance Race with a Change of Track

For the Chinese semiconductor industry, which faces continuous constraints in obtaining advanced processes, the Tao Law provides a feasible path to continuously improve performance without relying on extreme ultraviolet lithography (EUV) machines. It shifts the focus of global semiconductor competition from "who can buy the most advanced lithography machine" to "whose system architecture design is better", which is exactly the traditional strength of China's chip design field.

At the industry level, applying the Tao Law means that domestic wafer fabs do not need to blindly invest in the money - burning competition for 2 - nanometer and 1 - nanometer processes. Based on mature processes (such as 7 - nanometer and 5 - nanometer), through architectural innovations such as 3D stacking, logic folding, and advanced packaging, it is entirely possible to achieve the performance equivalent to that of advanced processes. This does not mean encouraging the abandonment of the pursuit of advanced processes but emphasizes a strategic rationality of parallel development on two tracks: when advanced processes are available, adding architectural optimization can achieve the performance limit; when advanced processes are not available, architectural innovation is the bottom - line for survival. The real value of the Tao Law lies in redefining the mature process as a "high - performance process", thereby revitalizing the existing investment of tens of billions of dollars in domestic wafer fabs.

At the investment level, the Tao Law is redefining the valuation logic of semiconductor enterprises. In the future, when evaluating a chip company, one cannot simply focus on the single indicator of "how many nanometers" but must pay attention to its system - level optimization capabilities, including architectural design level, software - hardware collaboration efficiency, advanced packaging technology reserves, and Chiplet interconnection solutions. Links that were previously on the periphery of the industrial chain, such as hybrid bonding, TSV (Through - Silicon Via), back - side power delivery, and optical I/O (such as Huawei's Hi - ONE technology), will see a re - evaluation of their value. For investors, a new screening framework needs to be established: focus on whether the enterprise has quantifiable data on reducing the τ value and whether it has the organizational ability for cross - domain collaboration, rather than just looking at the technology roadmap on the PPT.

At the enterprise methodology level, the Tao Law provides a transferable systematic thinking. Its essence is that when the physical limit or resource constraint cannot be broken through, instead of continuing to focus on a single dimension (such as size or cost), one should change to an optimizable core variable (such as time, efficiency, or collaboration). This idea of reconstructing the optimization goal under constraints has reference significance for other high - tech manufacturing industries and even enterprise management. At the same time, it emphasizes not a single - point technological breakthrough but the coordinated optimization of the four layers of devices, circuits, chips, and systems, which is similar to the "end - to - end process optimization" in enterprise management, requiring the breaking down of departmental barriers and the establishment of cross - domain joint teams.

At the technology cooperation level, He Tingbo clearly stated: "The future definitely belongs to open cooperation. Under the path of the Tao Law, we look forward to close cooperation with global scientists, engineers, and industry partners." This means that the Tao Law is not a closed system of Huawei but a technological ecosystem that is expected to be open to industry chain partners. Once relevant standards, IP cores, and reference designs are released, it will greatly lower the adoption threshold for small and medium - sized chip design enterprises and accelerate the prosperity of the entire ecosystem.

III. How Do International Peers View It: The Name and the Reality of the Law

For an industry evolution principle to rise from "a company's methodology" to "industry consensus", it needs to cross two thresholds: one is the independent reproduction in the technical community, and the other is the actual following in the industrial ecosystem. The reason why Moore's Law holds is not because Gordon Moore's paper in 1965 was so wonderful, but because in the following six decades, the entire semiconductor industrial chain, from lithography machine manufacturers, material suppliers, EDA tools, design companies to foundries, has jointly invested and iterated at this pace, turning it from an empirical observation into an industrial contract.

The Tao Law is currently still before the first threshold. Reuters reported that the performance data disclosed by Huawei this time has not been independently verified by a third party. The baselines (i.e., the specific parameters of the "flat - laid design in the same process") for the key indicators such as the 53.5% increase in density and 41% increase in energy efficiency given in He Tingbo's speech have not been made public. This does not mean that the data is in doubt. According to academic conventions, such assertions usually need to be reproduced at peer - reviewed conferences or in journals before they can enter the scope of industry consensus.

At the same time, it should be noted that overseas giants are actually advancing their own "system - level optimization" routes in a similar direction. TSMC's CoWoS, SoIC advanced packaging and 3DFabric roadmap, Intel's Foveros Direct hybrid bonding and back - side power delivery (PowerVia), and Samsung's X - Cube 3D stacking are all essentially aiming for performance in terms of "system - level density and energy efficiency" without relying on further breakthroughs in geometric scaling. In other words, "replacing simple geometric scaling with system optimization" is not a unique judgment of China but a global consensus in the post - Moore era. The uniqueness of the Tao Law does not lie in the direction choice but in integrating this direction into a quantifiable engineering methodology with the "time constant τ" as the core variable, and backing it up with 381 mass - produced chip models in six years.

This difference determines the reasonable expectation for the Tao Law: It is an engineering paradigm supported by industrial evidence, but it may not directly match the position of Moore's Law in industrial history. Giving it either too low an evaluation ("just Huawei's internal narrative") or too high an evaluation ("China will define global semiconductor rules from now on") will deviate from the actual significance of this release.

IV. What Should Be Noted When Applying the Tao Law

However, applying the Tao Law is by no means a simple technological slogan but a systematic change involving the reconstruction of methodology, the re - allocation of the industrial chain, and the reset of the valuation logic. If some constraint conditions are ignored in practice, it is easy to fall into the traps of concept hype or path dependence.

1. Technical implementation: Beware of the illusion of "single - point breakthrough"

The biggest application threshold of the Tao Law lies in the systematic integration ability rather than the advancement of a single technology. Logic folding is the most recognizable technology in this system. However, if the parasitic capacitance of the underlying devices and the interconnection resistance are not optimized synchronously, the high - density wiring after folding will actually exacerbate signal crosstalk and out - of - control power consumption. In other words, without the foundation of compressing the τ value at the device layer first, the folding at the circuit layer only changes the bottleneck from "routing length" to "thermal density". The data of 381 mass - produced chip models in six years publicly disclosed by Huawei is itself visible evidence of this systematic integration ability. Talking about logic folding without this integration ability is like building a building on quicksand.

Similarly, beware of the illusion of "single - point breakthrough" at the organizational level. The serial model of "finalizing the hardware first and then adapting the software" in traditional chip design needs to be replaced by the software - hardware collaboration required by the Tao Law. This means that architects, circuit designers, compiler teams, and process engineers must work in parallel from the project's inception. For most domestic chip design companies, this in - depth collaboration involves not a technical problem but an organizational ability problem: whether the departmental barriers, talent structure, and cross - domain decision - making mechanism can be opened up determines whether this paradigm can be truly applied.

2. Industrial strategy: Abandon the mentality of overtaking on a curve and adhere to long - termism

The Tao Law is a path verified by Huawei through six years and 381 mass - produced chip models, which reveals a cruel reality: There is no shortcut to establishing a new paradigm. Some domestic manufacturers may misinterpret the Tao Law as "no need to invest in advanced processes anymore", which is dangerous. Advanced processes and architectural innovation are not an either - or choice but a complementary relationship. At the same time, the industry and the capital market have long regarded "how many nanometers" as the only measure of technological advancement. When applying the Tao Law, new performance evaluation dimensions must be established, such as computing power density per unit power consumption, end - to - end latency, and system energy - efficiency ratio (Perf/Watt). If the old measure is still used to evaluate the new paradigm, it will lead to a serious distortion of resource allocation. Importantly, from the architectural theory to mass - produced chips and then to ecological software adaptation, the complete cycle often takes more than five years. This requires enterprises to have the ability to manage cash flow through the cycle and also requires capital providers to abandon the expectation of "quick and easy" returns.

3. Ecosystem construction: Don't work in isolation. Open standards determine survival

He Tingbo particularly emphasized open cooperation in her speech, which is by no means just a formality. If the Tao Law becomes a "black - box" technology exclusive to Huawei, its industrial value will be greatly reduced. For technologies such as logic folding, Chiplet interconnection, and Lingqu Bus to be widely adopted by the industrial chain, open interface standards and interoperability specifications must be established. Otherwise, if each manufacturer acts independently, it will lead to serious fragmentation of the ecosystem. A deeper challenge lies in the EDA toolchain. Most of the existing electronic design automation tools are based on the planar optimization logic of Moore's Law. The 3D architecture and temporal scaling optimization of the Tao Law require brand - new layout and routing algorithms, timing analysis models, and physical verification tools. If domestic EDA fails to keep up synchronously, architectural innovation will