The "fire" of AI has spread to analog chips.

It took humans about 100 years to miniaturize the vast power grid into vacuum tubes and integrated circuits, thus initiating the digital age. However, in the era of large models, the issue of electricity has pulled the digital system back into the physical world. The stronger the computing power and the more complex the system, the more important the simulation becomes.

On May 20th, NVIDIA announced its financial results for the first quarter of fiscal year 2027, ending on April 26th, 2026. Its single - quarter revenue reached $81.6 billion, a year - on - year increase of 85%. Among them, the data center revenue reached $75.2 billion, a year - on - year increase of 92%. The same goes for the storage side. In the second quarter of 2025, SK Hynix stated that the company was planning to increase its advanced chip manufacturing expenditure, mainly investing in HBM - related equipment, and said that the annual HBM sales were expected to double compared to the previous year.

The popularity of AI has made NVIDIA the most prominent company in the global semiconductor industry and has also made high - bandwidth memory one of the most scarce resources in AI servers. The first wave of AI dividends has gone to GPUs and HBMs. Meanwhile, we can see that the second wave of dividends is spreading to analog chips.

Recently, ADI acquired Empower Semiconductor for $1.5 billion in cash, sending a clear signal: the competition in the AI industry chain is moving from the obvious computing power segments such as GPUs and HBMs to the underlying support segments such as power supply, power, and signal integrity. Analog chips are no longer just background devices but are becoming a key variable for the continued expansion of AI infrastructure.

The end of AI is not just about computing power but also about energy. And the control of energy and signals ultimately depends on simulation.

Computing Power Races Ahead, Power Supply in Crisis

When AI systems evolve from single machines to racks, from ten - thousand - card clusters to one - hundred - thousand - card or even one - million - card clusters, the "computing power bucket" of digital chips is severely restricted by physical laws.

The "power shortage" in data centers is changing from a prediction to an imminent crisis.

The International Energy Agency (IEA) pointed out in its "Energy and AI" report that in 2024, the global data center power consumption was approximately 415 TWh, accounting for about 1.5% of the global power consumption. By 2030, the data center power consumption is expected to more than double, reaching about 945 TWh. The IEA also specifically noted that AI is one of the most important driving forces for this growth. The power consumption of accelerated servers is expected to increase by 30% annually on average and contribute nearly half of the net increase in global data center power consumption.

The Stargate project promoted by OpenAI, Oracle, and SoftBank can also be regarded as a landmark case of this trend. In September 2025, OpenAI disclosed that after adding five new AI data center sites in the United States, along with projects like Abilene and CoreWeave, the planned capacity has approached 7 GW. The investment in the next three years will exceed $400 billion, moving towards the previously announced commitments of $500 billion and 10 GW.

The bottleneck of AI systems is no longer just about "whether a faster core can be built" but has shifted to issues such as power distribution, power consumption conversion, signal integrity, and heat dissipation limits.

Without a good power supply, computing power is just a castle in the air.

The 800V DC Architecture Drives a Vertical Power Supply Revolution

This is why NVIDIA has started to promote the 800V DC architecture on its own.

In 2025, NVIDIA proposed an 800V DC power supply architecture for the next - generation AI Factory. Its official technical blog pointed out that the traditional 54V rack power supply, originally designed for kW - level racks, is not suitable for the upcoming MW - level AI racks. NVIDIA plans to promote the 800V DC data center power supply infrastructure starting from 2027 to support IT racks of 1 MW and above.

Why move from 48V/54V to 800V? It's a pure physical and engineering mathematics problem. According to Joule's law: P = IxV, Ploss = I²xR. When the rack power (P) soars from dozens of kW to over 1 MW, if the low - voltage 54V power supply is still used, the current (I) will reach an astonishing tens of thousands of amperes.

A huge current means extremely high transmission losses (proportional to the square of the current). The traditional power supply method is more of a horizontal power supply: the power module is placed at a certain position on the motherboard or accelerator card, and the current flows horizontally to the processor core through paths such as the PCB copper layer, vias, and package solder balls. However, when the current reaches hundreds of amperes or higher, this seemingly short path will cause obvious resistance losses, voltage drops, and heat generation.

As the current of GPUs (such as the Blackwell or even the next - generation architecture) approaches over 1000A, the power supply faces two major problems: the first is the transient response delay. When the GPU is fully loaded instantaneously, if the power supply is far away, the voltage will collapse instantly. The second is the parasitic resistance loss. Horizontal power supply (leading wires from the edge of the PCB to the center of the chip) will cause a serious voltage drop.

NVIDIA pointed out that in the scenario of a single rack with 1 MW of power, if the 54V architecture is used, the weight of the copper bars required for transmitting the current alone will be as high as 200 kg, which not only takes up precious server space but also makes wiring impossible. After moving to 800V DC, the current drops significantly, and the problems of copper consumption and space pressure are easily solved. NVIDIA's envisioned Kyber rack architecture uses high - voltage DC for centralized transmission and reduces the voltage to below 12V in one step through a high - transformation - ratio converter near the computing nodes. NVIDIA claims that this single - stage conversion scheme reduces the area by 26% compared to the traditional multi - stage conversion.

This is not a minor adjustment but a change at the power supply architecture level. It drives the demand for vertical power supply and near - core power supply.

Vertical power supply can be said to be the top - notch power supply technology in the HPC field. The integrated voltage regulator (IVR) and silicon capacitors are directly built into the chip package, or even stacked directly below the GPU. Through micro - bumps, the current is vertically injected into the wafer core like a "syringe". The power supply technology and chip packaging technology are completely integrated here.

The value of vertical power supply lies in compressing this "last path". It attempts to move power conversion, decoupling capacitors, and power integrity management closer to the load, and even send the current more directly to the vicinity of the computing core through a low - impedance path below the package or the chip. In this way, the system can reduce the voltage drop and heat loss caused by horizontal power supply and improve the transient response ability when the load changes rapidly.

Now, NVIDIA is working with giants such as ADI, Infineon, MPS, Navitas, onsemi, Renesas, ROHM, ST, and TI. They discuss together at the early stage of chip design "how this power supply architecture should be designed and how much space should be reserved for the power supply inside the package". The power supply is no longer a peripheral circuit; it is the underlying architecture of the computing power infrastructure itself.

ADI's Acquisition of Empower:

Securing the Ticket for "Near - Core Power Supply"

In NVIDIA's 800V ecosystem, ADI has recently made a significant investment.

On May 19th, ADI announced that it would acquire Empower Semiconductor for $1.5 billion in cash. ADI publicly stated that it aims to become the "Grid - to - Core" power supply partner for hyperscalers (ultra - large - scale data centers) and AI chip manufacturers.

The so - called Grid - to - Core can be understood as a complete power supply link that starts from the power entrance of the data center, covers high - voltage power distribution, rack power supply, server power supply, and board - level power supply, and finally reaches the vicinity of the GPU/ASIC core.

Empower is the key for ADI to achieve this goal. The core advantage of Empower that attracts ADI is near - core power supply and vertical power supply.

Empower's core technologies are IVR (integrated voltage regulator) and silicon capacitors. It can integrate the power management module directly at the silicon level, and even place it directly below the GPU chip in a 3D packaging form for "vertical power supply". This helps customers reduce the board area occupied by the power supply by up to 4 times and is expected to reduce the computing power consumption in data centers by 10% to 15%.

To understand the importance of this approach, Vicor is a good reference.

In the field of vertical power supply, Vicor is an early representative manufacturer that systematized the relevant architecture. Its underlying concept is the Factorized Power Architecture (FPA), which means disassembling the traditional power conversion process into different functional modules and then completing efficient conversion and current multiplication through high - density modules.

In terms of the power supply method close to the processor, Vicor mainly proposes two types of paths:

LPD, Lateral Power Delivery: Place the power module around the processor and supply power to the processor from the side.

VPD, Vertical Power Delivery: Place the power module further below the processor or near the package to shorten the current path vertically.

Vicor's official data shows that its architecture can combine LPD and VPD to reduce the power supply impedance of the "last inch". The relevant solution can reduce the motherboard resistance by up to 50 times and reduce the number of processor power supply pins by more than 10 times.

Empower's specific approach is not exactly the same as Vicor's, but the direction is the same: the power supply is moving from the board level to the vicinity of the package, from horizontal power supply to near - load or vertical power supply, and from single - device competition to system - level power supply architecture competition.

Cluster "Position - Grabbing" by Analog and Power Manufacturers

Traditional general - purpose power supply chips (PMIC) compete in terms of cost, scale, and shipment volume. In contrast, HPC power supplies compete in terms of extreme materials science, topological structure innovation, and topological control algorithms (digital power supply control). This is why in the past year, the entire semiconductor industry has been so crazy about mergers, acquisitions, and position - grabbing of high - performance power supply companies. Whoever can gain a foothold in the high - end HPC power supply field will get the ticket to the most profitable and high - barrier market in the AI era.

Facing the disruptive business opportunities brought by the 800V high - voltage direct current, 48V architecture, high - density modules, and near - core power supply, global analog and power semiconductor manufacturers are showing their skills and engaging in cluster - style position - grabbing around the next - generation AI power supply architecture. Generally speaking, this competition is forming several different technical routes.

TI & ST: Reducing the Number of Conversion Stages

Texas Instruments (TI) follows the route of "high density and few stages". In March 2026, TI and NVIDIA demonstrated a complete 800V solution. This solution only requires two conversion stages from 800V to the GPU core power supply: an 800V to 6V isolated bus converter and a multi - phase buck solution from 6V to below 1V. Among them, the 800V to 6V DC/DC bus converter uses an integrated GaN power stage, with a peak efficiency of 97.6% and a power density of over 2000W/in³.

ST also bets on two - stage conversion. In March 2026, ST launched an 800V direct - to - 6V/12V architecture. ST said that the 800V to 6V path can bring the 6V bus closer to the GPU, reducing the number of conversion stages, copper usage, and resistance losses, and improving transient performance.

The near - core power supply logic of TI & ST is not exactly the same as that of ADI + Empower, but the direction is the same: the closer to the computing core, the higher the value of the power supply.

MPS: High - Density Modular Power Supply

MPS is an indispensable player in the AI/HPC power supply battlefield. It does not simply provide a single DC/DC chip. Instead, it entered the fields of high - density power modules, 48V architecture, intelligent power integration, and digital control earlier, focusing on the power supply needs of data centers and AI GPUs.

This is the real difficulty in the AI power supply track: it is not about "whether a power supply chip can be made" but about whether a large amount of current can be delivered to the vicinity of the GPU/ASIC with high efficiency, fast transient response, and low heat loss within the limited board - level space. This tests the comprehensive capabilities of chip design, packaging, layout, thermal design, and customer platform verification.

Infineon & Renesas: Leveraging the Advantages of Third - Generation Semiconductors and Control

Infineon starts from its strengths in "high voltage, large current, and high reliability". They focus on using SiC/GaN devices, advanced drivers, and system - level control algorithms to ensure that the 800V high - voltage power supply is stable at the first level when entering the data center.

Renesas enters the 800V ecosystem with GaN and power control. In October 2025, Renesas announced its support for NVIDIA's 800V DC AI data center architecture. Its solution focuses on GaN power devices, MOSFETs, controllers, and drivers. Renesas said that GaN devices help with fast switching, reduce energy losses, and improve thermal management. Its GaN solution can support DC/DC conversion from 48V to 400V and can be stacked up to 800V. The efficiency of the converter based on the LLC DCX topology can reach up to 98%.

Another Overlooked Analog Battlefield:

High - Speed Signal Chain

In addition to power management, AI has also ignited another niche track in analog chips - the high - speed signal chain (Retimer/Redriver chips).

The essence of an AI server is not just to stuff more GPUs into a cabinet but to create a high - throughput, low - latency, and scalable data system among GPUs, CPUs, DPUs, network cards, SSDs, CXL memories, and switch chips. As PCIe 6.0 increases to 64 GT/s and PCIe 7.0 aims for 128 GT/s, signals will be severely distorted after traveling a few centimeters on the PCB. This requires the server motherboard to be densely populated with high - performance analog mixed - signal chips to repair, compensate, and regenerate the signals, such as Retimers, Redrivers, Clock Buffers, Jitter Attenuators, CDRs, PLLs, high - speed SerDes analog front - ends, etc.

These products are exactly the areas where traditional analog chip manufacturers have long - term accumulated capabilities.

Take TI as an example. It has relatively complete signal conditioning products and technical reserves in the direction of PCIe Redriver/Retimer. TI's official data shows that its PCIe 5.0 linear Redriver is designed for high - speed interfaces such as 32Gbps PCIe 5.0, CXL, and UPI 2.0. It can provide a maximum CTLE boost of 24dB, an ultra - low latency of 100ps, and support PCIe bus widths of x4, x8, and x16.

Renesas mainly focuses on clock and timing chips. The high - speed links in AI servers not only require clean data channels but also low - jitter clocks. Renesas launched a complete PCIe clock solution for data centers and network infrastructure as early as the PCIe Gen5 stage. In the PCIe Gen6 stage, it launched a product portfolio of clock buffers and multiplexers that meet the PCIe Gen6 specifications. The new devices are designed for low - jitter clock distribution in server, high - performance computing, and data center platforms.

ADI's data center solutions cover power management, optical interconnection control, and sensing solutions in high - density servers, storage, and network systems. Its high - performance clock and jitter attenuator products have long served high - speed data converter, JESD204B, and other high - speed interface scenarios. For example, ADI's HMC7044 is a dual - loop integer N jitter attenuator used to provide ultra - low phase - noise clocks for high - speed data converters.

On the Microchip side, in 2025, Microchip announced the expansion of its product portfolio for AI data center connectivity, storage, and computing, emphasizing the need to meet the requirements of AI data centers for bandwidth, performance, security, and management capabilities.