IC Coder uses AI to solve pain points in chip verification and seeks financing

The Chip Design and Verification Stage Remains a Bottleneck for R&D Efficiency

There has long been an efficiency bottleneck in the chip design and verification stage. FPGA and digital IC front - end R&D usually involve understanding requirements, disassembling the architecture, writing RTL, building test platforms, conducting simulation verification, analyzing waveforms, locating problems, and making multiple rounds of modifications. The above processes highly depend on the experience of senior engineers, resulting in long R&D cycles and high collaboration costs. In particular, the verification and debugging stages often consume a large amount of time. The business plan reveals that SoC verification may consume more than 70% of the development cycle, and it takes an average of 16 to 20 hours to locate a single bug. For chip design companies, FPGA R&D enterprises, scientific research institutions, and university laboratories, how to shorten the cycle from requirements to verifiable engineering results is becoming a key issue affecting R&D efficiency and project delivery certainty.

IC Coder, launched by Chengdu Pengye Jiantu Technology, is an AI intelligent agent platform built around this pain point. Different from general - purpose code assistants, IC Coder is not only aimed at the single task of "writing code", but at the entire process of chip design and verification, covering requirements analysis, Spec generation, RTL writing, automatic TestBench generation, simulation verification, waveform analysis, EDA interaction, and problem repair. The project team positions it as a professional - level AI R&D platform for FPGA development, digital IC front - end design, chip function verification, IP core development, and SoC subsystem prototype verification, hoping to let AI enter the main process of real - world engineering from an auxiliary Q&A tool.

From Code Generation to Engineering Closed - Loop

The core capabilities of IC Coder come from its self - developed chip design special model and Multi - Agent multi - intelligent agent system. The platform first disassembles the natural - language requirements input by users to form a structured Spec, and then further generates RTL code, TestBench, simulation tasks, and waveform analysis results. Compared with general - purpose AI that generates a piece of code and then leaves it to engineers to judge, IC Coder emphasizes the closed - loop ability of "generation - verification - iteration", that is, through the feedback of compilers, simulators, waveform analysis tools, and EDA tools, it continuously discovers problems and promotes code repair.

At the engineering toolchain level, IC Coder supports docking with mainstream EDA tools such as Vivado and TD, and can read feedback information such as synthesis, layout and routing, timing analysis, and operation logs through scripts. The waveform analysis ability is used to parse VCD files, track signal changes, and locate potential logical problems, so that the AI output is no longer limited to text results but combined with engineering evidence. For enterprise customers, the platform also provides private deployment, intranet operation, local model delivery, and permission management to meet the requirements of chip R&D for code security, data isolation, and process control.

A typical case disclosed by the project team shows that in the industrial camera image acquisition and DDR cache control subsystem project, the traditional model requires a team of about 5 people and 60 working days to complete the relevant development and verification; after using IC Coder, the project was compressed to a team of about 2 people and 3 working days to complete the phased tasks. This data comes from the project team's internal cases, and more projects still need to be continuously verified in scenarios of different complexities, but it reflects the efficiency - improvement potential of AI closed - loop tools in repetitive coding, test platform generation, simulation feedback, and problem location.

Commercialization Verification and Financing Plan

In terms of market positioning, IC Coder targets the cross - market of "industrial software, chip R&D, and AI Agent". The industry data cited in the business plan shows that the global Electronic System Design industry was worth about $19.25 billion in 2024, and there are more than 3,600 chip design companies in China. The project team believes that chip design companies, FPGA and digital hardware R&D enterprises, scientific research institutions, university laboratories, and innovative R&D teams are the core customer groups that IC Coder focuses on serving in the early stage. According to its calculations, the number of domestic core institutional customers that can be served is expected to exceed 1,000 in the next 3 to 5 years. The combined revenue from platform authorization, private deployment, operation and maintenance implementation, extended seats, professional design services, and AI customized R&D will constitute the main commercial space.

In terms of business model, IC Coder adopts a parallel approach of platform authorization, private deployment, cloud service subscription, industry solutions, and professional design services. Enterprise customers pay more attention to data security, process adaptation, and R&D efficiency improvement. Therefore, private deployment, local model delivery, and enterprise - level delivery services will be the focus of early - stage revenue; for universities and individual developers, the user coverage will be expanded through the Web terminal, plug - in terminal, course cooperation, and lightweight subscription to precipitate real requirements and engineering data. In the long run, the project team also plans to extend from the FPGA R&D platform to directions such as digital IC front - end, SoC subsystems, edge - side intelligent chips, NPU modules, and IP authorization.

According to the project team, about three months after the release of IC Coder, it has reached more than 10 leading semiconductor enterprise customers, more than 50 mid - tier customers, covered more than 30 universities, with a MAU of more than 5,000, and a cumulative saving of more than 100,000 hours of development time. The project has become an official ecological partner of ANlogic's "University Program" and has made phased progress in university laboratory co - construction, offline training, enterprise customer reach, and procurement conversion. In terms of the team, the founder, Cai Jietao, has long been deeply involved in the FPGA and digital IC fields, and the core team covers capabilities in chip R&D, AI productization, platform engineering, private delivery, and university ecological cooperation.

In terms of financing, the project team has self - invested 5 million yuan and currently plans to launch an angel - round financing of 8 million yuan. The funds will be mainly used for strengthening the special model for chip design and verification, improving the IDE/plug - in/Web - end products, converting B - end private - deployment customers, increasing C - end users, and building an industry knowledge base. For investors, the core attraction of IC Coder is that the trend of AI Coding has been verified in the software development field, while the chip R&D, as a professional scenario with higher thresholds, high customer unit prices, and strong security requirements, still lacks a mature platform - type product. IC Coder tries to combine vertical models, intelligent agent workflows, EDA toolchain collaboration, and enterprise - level delivery capabilities during this window period to become an early participant in the AI - driven chip R&D infrastructure.