Is it possible to manufacture 3nm chips without EUV?

In the semiconductor evolution over the past few decades, it can be said that every miniaturization has relied on the support of lithography capabilities. From DUV to EUV, from 193nm to 13.5nm, and then to High-NA EUV, the entire industrial chain has been evolving around a core variable - how to use shorter wavelengths to etch finer lines on silicon wafers. However, an undeniable fact is that lithography is becoming overly expensive, overly complex, and overly irreplaceable.

As the process technology continues to shrink, the price of wafers has been rising linearly. The price of 5nm/3nm wafers has exceeded $20,000, and it is predicted that the price of a single 2nm wafer will reach a record high of $30,000. The core reason for the soaring price is the extremely high difficulty of patterning in advanced processes. The price of an EUV lithography machine exceeds $150 million, and the delivery cycle is more than a year. High-NA EUV is even more expensive, and there is only one global supplier, ASML. Against the backdrop of the explosion of AI computing power, this bottleneck is being further magnified.

It is against this backdrop that AlixLabs, a startup from Lund, Sweden, has proposed a completely different path: instead of etching the patterns, it "splits" them. The company plans to use their APS (Atomic Layer Etching Pitch Splitting) technology to attempt to achieve 5nm or even 3nm patterning without EUV.

The origin of the technology, an accidental discovery in the laboratory

Around Christmas in 2015, in the laboratory of Lund University in Sweden, an otherwise unremarkable experiment unexpectedly opened up a new technological path.

Researchers at Lund University in Sweden were trying to reduce the size of surface nanowires when they observed an abnormal phenomenon: these nanowires not only became thinner but also "split" into two finer structures. Chief researcher Jonas Sundqvist quickly realized that this was extraordinary. For those familiar with semiconductor processes, the significance of this phenomenon is extremely clear: it is equivalent to a natural multiple patterning. This discovery provides a theoretical possibility for achieving miniaturization (Scaling) without lithography.

Atomic-level etching splits one line into two

In the era when EUV was not yet mature, the industry relied on SADP (Self-Aligned Double Patterning) and SAQP (Self-Aligned Quadruple Patterning) to continue to promote miniaturization. However, the cost of these solutions is an exponentially increasing process complexity.

In 2019, Jonas Sundqvist founded Alixlabs with co-founders Amin Karimi and Stefan Svedberg. The company is headquartered in Lund. Then they continued to develop this technology.

AlixLabs' core technology is an extension of Atomic Layer Etching (ALE). Similar to the more mature Atomic Layer Deposition (ALD), ALE is also a self-limiting process, but in the opposite direction: ALD adds atoms layer by layer, while ALE removes atoms layer by layer.

This atomic-level subtraction brings three key capabilities: First, the ultimate size control ability. Each etching step is carried out at the atomic scale, making it possible to control the CD (Critical Dimension) in the sub-10nm range. Second, the self-alignment ability of the morphology. The sidewalls of the nanostructure itself can act as a natural mask during the etching process. Third, the fidelity of the three-dimensional structure. Compared with traditional etching, ALE is more friendly to complex structures (such as FinFET, GAA).

Bypassing EUV, what about the horizontal geometry of APS?

On this basis, AlixLabs proposed the core process: APS (Atomic Pitch Splitting). Its essence is to use ALE to copy and split the existing patterns to achieve density doubling. In terms of results, it is similar to SADP/SAQP, but the path is completely different: EUV directly etches with a shorter wavelength, which is costly; SADP/SAQP involves multiple lithography and deposition steps, with complex processes; APS drives splitting through etching, and the process is relatively simplified.

As shown in the figure below, to achieve the same result of halving the pitch (40nm → 20nm), the traditional SADP requires multiple steps such as lithography, photoresist processing, oxide layer deposition, spacer etching, hard mask etching, and cleaning. However, AlixLabs' technology only has two steps: lithography and APS. Moreover, the quality of the structure produced by APS is good, and the line uniformity and verticality are not inferior to those of traditional processes.

Comparison between APS and traditional SADP

Alixlabs also demonstrated how APS can be embedded in the real process flow. The general process is: NIL (Nanoimprint Lithography) → Residue cleaning → Pattern transfer → Photoresist removal → APS. That is, first use traditional methods to create a structure that is not fine enough, and then use APS to perform atomic layer etching splitting on the existing structure. As a result, it can achieve a direct halving from 205 nm to 109 nm without lithography.

How APS is embedded in the real process flow

Moreover, it is very important to note that APS is not a "local optimization tool" limited to a specific node, but a general structure scaling ability. Experimental results under different initial pitches from 100nm to 20nm show that APS can stably achieve about a 2-fold pitch compression and simultaneously reduce the line width.

100nm → 54nm → 32nm → 20nm, each column achieves "approximately halving the pitch"

In 2024, APS patterning based on EBL was successfully achieved on a silicon (Si) substrate, realizing a leap from compound semiconductors to mainstream silicon-based semiconductors. From the experimental results, APS has achieved a 10nm-level CD and a 12.5nm-level half-pitch on silicon-based materials. This indicator is already approaching the capability range of Low-NA EUV. Although High-NA EUV still has an advantage in terms of extreme size and line edge roughness, the combination of "close to EUV performance + significantly lower cost" demonstrated by APS makes it have the potential to become an alternative solution for some process layers.

APS vs the three most mainstream advanced process paths in the industry

What is more subversive is that APS is not only capable of single pitch splitting but also has the "hierarchical scaling ability" that can be repeatedly invoked. Through two APS treatments, the original structure of about 95nm can be compressed to the 20nm level, which is equivalent to the effect achieved by traditional quadruple patterning (SAQP), but the path is greatly simplified. This means that the "multiple patterning" in advanced processes can be transformed from an engineering problem relying on complex process stacking to a physical process problem based on atomic layer etching. The 5nm-level structure and the atomic arrangement close to the lattice scale shown on the right side of the figure below also indicate that this technology has approached the material limit, providing a new possible path for future sub-5nm and even more advanced nodes.

APS can not only "×2" but also "×4"

It is reported that AlixLabs has completed the development of a 300mm APS device and achieved stable operation in its clean room in Lund.

APS is a powerful supplement to Nanoimprint Lithography (NIL) and can expand the resolution of dense line patterns. It can be used as an alternative to traditional multiple patterning technologies (such as SADP, SAQP, and LELE), with the potential to reduce costs, improve resolution, and enhance sustainability.

"We estimate that APS is expected to reduce the manufacturing cost of cutting-edge logic and memory wafers by up to 40% per mask layer while improving production efficiency," Sundqvist added.

Backed by big manufacturers, key breakthroughs in industrialization

This startup has collaborated with Intel and recently successfully demonstrated a 12.5-nanometer half-pitch fin structure on bulk silicon without using Extreme Ultraviolet Lithography (EUV) technology. These dimensions are the same as those of current 3-nanometer cutting-edge logic chips. "Our mission is to build equipment that can help companies that cannot use EUV equipment to scale down production to 5 nanometers and below. By eliminating the dependence on EUV lithography technology, we provide the industry with a path to more sustainable and cost-effective high-density chip production," Sundqvist said.

In 2025, AlixLabs collaborated with UMC (United Microelectronics Corporation) for a wafer-level demonstration and successfully achieved a 19nm half-pitch using immersion argon fluoride (ArFi) lithography technology.

According to AlixLabs' latest outlook in 2026, the application of APS has extended to every key corner of semiconductor manufacturing. In addition to the classic line pitch splitting, it is tackling three new high grounds: through the precise processing of Vias, APS solves the bottleneck of multi-layer circuit interconnection. From the hard Hard Mask to the challenging Photoresist, APS will prove the extremely high flexibility of Atomic Layer Etching (ALE).

To subvert the traditional lithography model, having only the process is not enough; matching equipment support is essential. The equipment roadmap disclosed by AlixLabs shows that its commercialization process has entered the fast lane: The Alpha-level device can already perform 300mm wafer demonstrations, achieving a physical breakthrough from 0 to 1 and enabling spot supply; the Beta-level tool with automated cluster capabilities will be delivered in Q3 2026, which will be the ticket for its technology to enter the leading line of semiconductor foundries; the Gamma platform is aimed at HVM (High-Volume Manufacturing) and is currently in the conceptual design stage.

Conclusion

Generally speaking, for wafer fabs that cannot obtain EUV quotas or cannot afford its high capital and operating costs, APS provides not only an alternative solution but also a realistic "second path".

Of course, APS will not replace EUV in the short term. For the most advanced nodes, especially the extreme sizes targeted by High-NA EUV, lithography is still an irreplaceable core tool. However, in a large number of non-critical layers and cost-sensitive application scenarios, APS is expected to become a more cost-effective solution and coexist with lithography technology in the long term.

This article is from the WeChat official account "Semiconductor Industry Observation" (ID: icbank), author: Du Qin DQ, published by 36Kr with authorization.